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Liu Yinglumag
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dt-bindings: display: lvds-data-mapping: Add 30-bit RGB pixel data mappings
Add "jeida-30" and "vesa-30" data mappings that are compatible with JEIDA and VESA respectively. Signed-off-by: Liu Ying <victor.liu@nxp.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20241104032806.611890-8-victor.liu@nxp.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Documentation/devicetree/bindings/display/lvds-data-mapping.yaml

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Device compatible with those specifications have been marketed under the
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FPD-Link and FlatLink brands.
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This bindings also supports 30-bit data mapping compatible with JEIDA and
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VESA.
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properties:
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data-mapping:
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enum:
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- jeida-18
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- jeida-24
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- jeida-30
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- vesa-24
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- vesa-30
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description: |
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The color signals mapping order.
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DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
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DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
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- "jeida-30" - 30-bit data mapping compatible with JEIDA and VESA. Data
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are transferred as follows on 5 LVDS lanes.
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Slot 0 1 2 3 4 5 6
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________________ _________________
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Clock \_______________________/
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______ ______ ______ ______ ______ ______ ______
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DATA0 ><__G4__><__R9__><__R8__><__R7__><__R6__><__R5__><__R4__><
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DATA1 ><__B5__><__B4__><__G9__><__G8__><__G7__><__G6__><__G5__><
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DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B9__><__B8__><__B7__><__B6__><
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DATA3 ><_CTL3_><__B3__><__B2__><__G3__><__G2__><__R3__><__R2__><
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DATA4 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
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- "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
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Data are transferred as follows on 4 LVDS lanes.
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DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
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DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
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- "vesa-30" - 30-bit data mapping compatible with VESA. Data are
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transferred as follows on 5 LVDS lanes.
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Slot 0 1 2 3 4 5 6
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________________ _________________
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Clock \_______________________/
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______ ______ ______ ______ ______ ______ ______
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DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
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DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
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DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
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DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
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DATA4 ><_CTL3_><__B9__><__B8__><__G9__><__G8__><__R9__><__R8__><
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Control signals are mapped as follows.
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CTL0: HSync

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