Skip to content

Commit e1fbfa4

Browse files
Ansueldavem330
Ansuel
authored and
davem330
committed
net: phy: aquantia: move MMD_VEND define to header
Move MMD_VEND define to header to clean things up and in preparation for firmware loading support that require some define placed in aquantia_main. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
1 parent d2213db commit e1fbfa4

File tree

3 files changed

+69
-69
lines changed

3 files changed

+69
-69
lines changed

‎drivers/net/phy/aquantia/aquantia.h

Lines changed: 69 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,75 @@
99
#include <linux/device.h>
1010
#include <linux/phy.h>
1111

12+
/* Vendor specific 1, MDIO_MMD_VEND1 */
13+
#define VEND1_GLOBAL_FW_ID 0x0020
14+
#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
15+
#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
16+
17+
/* The following registers all have similar layouts; first the registers... */
18+
#define VEND1_GLOBAL_CFG_10M 0x0310
19+
#define VEND1_GLOBAL_CFG_100M 0x031b
20+
#define VEND1_GLOBAL_CFG_1G 0x031c
21+
#define VEND1_GLOBAL_CFG_2_5G 0x031d
22+
#define VEND1_GLOBAL_CFG_5G 0x031e
23+
#define VEND1_GLOBAL_CFG_10G 0x031f
24+
/* ...and now the fields */
25+
#define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7)
26+
#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0
27+
#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1
28+
#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
29+
30+
/* Vendor specific 1, MDIO_MMD_VEND2 */
31+
#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421
32+
#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422
33+
#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423
34+
#define VEND1_THERMAL_PROV_LOW_TEMP_WARN 0xc424
35+
#define VEND1_THERMAL_STAT1 0xc820
36+
#define VEND1_THERMAL_STAT2 0xc821
37+
#define VEND1_THERMAL_STAT2_VALID BIT(0)
38+
#define VEND1_GENERAL_STAT1 0xc830
39+
#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL BIT(14)
40+
#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL BIT(13)
41+
#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN BIT(12)
42+
#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN BIT(11)
43+
44+
#define VEND1_GLOBAL_GEN_STAT2 0xc831
45+
#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15)
46+
47+
#define VEND1_GLOBAL_RSVD_STAT1 0xc885
48+
#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
49+
#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
50+
51+
#define VEND1_GLOBAL_RSVD_STAT9 0xc88d
52+
#define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
53+
#define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
54+
55+
#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
56+
#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
57+
58+
#define VEND1_GLOBAL_INT_STD_MASK 0xff00
59+
#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
60+
#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
61+
#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
62+
#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
63+
#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
64+
#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
65+
#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
66+
#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
67+
#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
68+
#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
69+
#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
70+
71+
#define VEND1_GLOBAL_INT_VEND_MASK 0xff01
72+
#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
73+
#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
74+
#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
75+
#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
76+
#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
77+
#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
78+
#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
79+
#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
80+
1281
#if IS_REACHABLE(CONFIG_HWMON)
1382
int aqr_hwmon_probe(struct phy_device *phydev);
1483
#else

‎drivers/net/phy/aquantia/aquantia_hwmon.c

Lines changed: 0 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -13,20 +13,6 @@
1313

1414
#include "aquantia.h"
1515

16-
/* Vendor specific 1, MDIO_MMD_VEND2 */
17-
#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421
18-
#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422
19-
#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423
20-
#define VEND1_THERMAL_PROV_LOW_TEMP_WARN 0xc424
21-
#define VEND1_THERMAL_STAT1 0xc820
22-
#define VEND1_THERMAL_STAT2 0xc821
23-
#define VEND1_THERMAL_STAT2_VALID BIT(0)
24-
#define VEND1_GENERAL_STAT1 0xc830
25-
#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL BIT(14)
26-
#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL BIT(13)
27-
#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN BIT(12)
28-
#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN BIT(11)
29-
3016
#if IS_REACHABLE(CONFIG_HWMON)
3117

3218
static umode_t aqr_hwmon_is_visible(const void *data,

‎drivers/net/phy/aquantia/aquantia_main.c

Lines changed: 0 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -91,61 +91,6 @@
9191
#define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a
9292
#define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b
9393

94-
/* Vendor specific 1, MDIO_MMD_VEND1 */
95-
#define VEND1_GLOBAL_FW_ID 0x0020
96-
#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
97-
#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
98-
99-
#define VEND1_GLOBAL_GEN_STAT2 0xc831
100-
#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15)
101-
102-
/* The following registers all have similar layouts; first the registers... */
103-
#define VEND1_GLOBAL_CFG_10M 0x0310
104-
#define VEND1_GLOBAL_CFG_100M 0x031b
105-
#define VEND1_GLOBAL_CFG_1G 0x031c
106-
#define VEND1_GLOBAL_CFG_2_5G 0x031d
107-
#define VEND1_GLOBAL_CFG_5G 0x031e
108-
#define VEND1_GLOBAL_CFG_10G 0x031f
109-
/* ...and now the fields */
110-
#define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7)
111-
#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0
112-
#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1
113-
#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
114-
115-
#define VEND1_GLOBAL_RSVD_STAT1 0xc885
116-
#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
117-
#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
118-
119-
#define VEND1_GLOBAL_RSVD_STAT9 0xc88d
120-
#define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
121-
#define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
122-
123-
#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
124-
#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
125-
126-
#define VEND1_GLOBAL_INT_STD_MASK 0xff00
127-
#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
128-
#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
129-
#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
130-
#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
131-
#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
132-
#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
133-
#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
134-
#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
135-
#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
136-
#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
137-
#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
138-
139-
#define VEND1_GLOBAL_INT_VEND_MASK 0xff01
140-
#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
141-
#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
142-
#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
143-
#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
144-
#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
145-
#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
146-
#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
147-
#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
148-
14994
/* Sleep and timeout for checking if the Processor-Intensive
15095
* MDIO operation is finished
15196
*/

0 commit comments

Comments
 (0)