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Sam Protsenkokrzk
Sam Protsenko
authored and
krzk
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clk: samsung: exynos850: Implement CMU_G3D domain
CMU_G3D clock domain provides clocks for Mali-G52 GPU and bus clocks for BLK_G3D. This patch adds next clocks: - bus clocks in CMU_TOP for CMU_G3D - all internal CMU_G3D clocks - leaf clocks for GPU, TZPC (TrustZone Protection Controller) and SysReg G3D_CMU_G3D clock was marked as CLK_IGNORE_UNUSED, as system hangs on boot otherwise. Reviewed-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20230223042133.26551-5-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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‎drivers/clk/samsung/clk-exynos850.c

Lines changed: 120 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,7 @@
3636
#define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
3737
#define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020
3838
#define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034
39+
#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1038
3940
#define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c
4041
#define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040
4142
#define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044
@@ -57,6 +58,7 @@
5758
#define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
5859
#define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c
5960
#define CLK_CON_DIV_CLKCMU_DPU 0x1840
61+
#define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1844
6062
#define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848
6163
#define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c
6264
#define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850
@@ -84,6 +86,7 @@
8486
#define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
8587
#define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028
8688
#define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c
89+
#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2040
8790
#define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044
8891
#define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048
8992
#define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c
@@ -116,6 +119,7 @@ static const unsigned long top_clk_regs[] __initconst = {
116119
CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD,
117120
CLK_CON_MUX_MUX_CLKCMU_CORE_SSS,
118121
CLK_CON_MUX_MUX_CLKCMU_DPU,
122+
CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
119123
CLK_CON_MUX_MUX_CLKCMU_HSI_BUS,
120124
CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD,
121125
CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD,
@@ -137,6 +141,7 @@ static const unsigned long top_clk_regs[] __initconst = {
137141
CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD,
138142
CLK_CON_DIV_CLKCMU_CORE_SSS,
139143
CLK_CON_DIV_CLKCMU_DPU,
144+
CLK_CON_DIV_CLKCMU_G3D_SWITCH,
140145
CLK_CON_DIV_CLKCMU_HSI_BUS,
141146
CLK_CON_DIV_CLKCMU_HSI_MMC_CARD,
142147
CLK_CON_DIV_CLKCMU_HSI_USB20DRD,
@@ -164,6 +169,7 @@ static const unsigned long top_clk_regs[] __initconst = {
164169
CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD,
165170
CLK_CON_GAT_GATE_CLKCMU_CORE_SSS,
166171
CLK_CON_GAT_GATE_CLKCMU_DPU,
172+
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
167173
CLK_CON_GAT_GATE_CLKCMU_HSI_BUS,
168174
CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD,
169175
CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD,
@@ -216,6 +222,9 @@ PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2",
216222
"oscclk", "oscclk" };
217223
PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3",
218224
"dout_shared0_div4", "dout_shared1_div4" };
225+
/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */
226+
PNAME(mout_g3d_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
227+
"dout_shared0_div3", "dout_shared1_div3" };
219228
/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */
220229
PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" };
221230
PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2",
@@ -283,6 +292,10 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
283292
MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p,
284293
CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2),
285294

295+
/* G3D */
296+
MUX(CLK_MOUT_G3D_SWITCH, "mout_g3d_switch", mout_g3d_switch_p,
297+
CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2),
298+
286299
/* HSI */
287300
MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p,
288301
CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1),
@@ -357,6 +370,10 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
357370
DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu",
358371
CLK_CON_DIV_CLKCMU_DPU, 0, 4),
359372

373+
/* G3D */
374+
DIV(CLK_DOUT_G3D_SWITCH, "dout_g3d_switch", "gout_g3d_switch",
375+
CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
376+
360377
/* HSI */
361378
DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus",
362379
CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4),
@@ -417,6 +434,10 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
417434
GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu",
418435
CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
419436

437+
/* G3D */
438+
GATE(CLK_GOUT_G3D_SWITCH, "gout_g3d_switch", "mout_g3d_switch",
439+
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0),
440+
420441
/* HSI */
421442
GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus",
422443
CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0),
@@ -992,6 +1013,102 @@ static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
9921013
.clk_name = "gout_clkcmu_cmgp_bus",
9931014
};
9941015

1016+
/* ---- CMU_G3D ------------------------------------------------------------- */
1017+
1018+
/* Register Offset definitions for CMU_G3D (0x11400000) */
1019+
#define PLL_LOCKTIME_PLL_G3D 0x0000
1020+
#define PLL_CON0_PLL_G3D 0x0100
1021+
#define PLL_CON3_PLL_G3D 0x010c
1022+
#define PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER 0x0600
1023+
#define CLK_CON_MUX_MUX_CLK_G3D_BUSD 0x1000
1024+
#define CLK_CON_DIV_DIV_CLK_G3D_BUSP 0x1804
1025+
#define CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK 0x2000
1026+
#define CLK_CON_GAT_CLK_G3D_GPU_CLK 0x2004
1027+
#define CLK_CON_GAT_GOUT_G3D_TZPC_PCLK 0x200c
1028+
#define CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK 0x2010
1029+
#define CLK_CON_GAT_GOUT_G3D_BUSD_CLK 0x2024
1030+
#define CLK_CON_GAT_GOUT_G3D_BUSP_CLK 0x2028
1031+
#define CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK 0x202c
1032+
1033+
static const unsigned long g3d_clk_regs[] __initconst = {
1034+
PLL_LOCKTIME_PLL_G3D,
1035+
PLL_CON0_PLL_G3D,
1036+
PLL_CON3_PLL_G3D,
1037+
PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER,
1038+
CLK_CON_MUX_MUX_CLK_G3D_BUSD,
1039+
CLK_CON_DIV_DIV_CLK_G3D_BUSP,
1040+
CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK,
1041+
CLK_CON_GAT_CLK_G3D_GPU_CLK,
1042+
CLK_CON_GAT_GOUT_G3D_TZPC_PCLK,
1043+
CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK,
1044+
CLK_CON_GAT_GOUT_G3D_BUSD_CLK,
1045+
CLK_CON_GAT_GOUT_G3D_BUSP_CLK,
1046+
CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK,
1047+
};
1048+
1049+
/* List of parent clocks for Muxes in CMU_G3D */
1050+
PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll" };
1051+
PNAME(mout_g3d_switch_user_p) = { "oscclk", "dout_g3d_switch" };
1052+
PNAME(mout_g3d_busd_p) = { "mout_g3d_pll", "mout_g3d_switch_user" };
1053+
1054+
/*
1055+
* Do not provide PLL table to PLL_G3D, as MANUAL_PLL_CTRL bit is not set
1056+
* for that PLL by default, so set_rate operation would fail.
1057+
*/
1058+
static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
1059+
PLL(pll_0818x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
1060+
PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL),
1061+
};
1062+
1063+
static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
1064+
MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
1065+
PLL_CON0_PLL_G3D, 4, 1),
1066+
MUX(CLK_MOUT_G3D_SWITCH_USER, "mout_g3d_switch_user",
1067+
mout_g3d_switch_user_p,
1068+
PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 4, 1),
1069+
MUX(CLK_MOUT_G3D_BUSD, "mout_g3d_busd", mout_g3d_busd_p,
1070+
CLK_CON_MUX_MUX_CLK_G3D_BUSD, 0, 1),
1071+
};
1072+
1073+
static const struct samsung_div_clock g3d_div_clks[] __initconst = {
1074+
DIV(CLK_DOUT_G3D_BUSP, "dout_g3d_busp", "mout_g3d_busd",
1075+
CLK_CON_DIV_DIV_CLK_G3D_BUSP, 0, 3),
1076+
};
1077+
1078+
static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
1079+
GATE(CLK_GOUT_G3D_CMU_G3D_PCLK, "gout_g3d_cmu_g3d_pclk",
1080+
"dout_g3d_busp",
1081+
CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1082+
GATE(CLK_GOUT_G3D_GPU_CLK, "gout_g3d_gpu_clk", "mout_g3d_busd",
1083+
CLK_CON_GAT_CLK_G3D_GPU_CLK, 21, 0, 0),
1084+
GATE(CLK_GOUT_G3D_TZPC_PCLK, "gout_g3d_tzpc_pclk", "dout_g3d_busp",
1085+
CLK_CON_GAT_GOUT_G3D_TZPC_PCLK, 21, 0, 0),
1086+
GATE(CLK_GOUT_G3D_GRAY2BIN_CLK, "gout_g3d_gray2bin_clk",
1087+
"mout_g3d_busd",
1088+
CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK, 21, 0, 0),
1089+
GATE(CLK_GOUT_G3D_BUSD_CLK, "gout_g3d_busd_clk", "mout_g3d_busd",
1090+
CLK_CON_GAT_GOUT_G3D_BUSD_CLK, 21, 0, 0),
1091+
GATE(CLK_GOUT_G3D_BUSP_CLK, "gout_g3d_busp_clk", "dout_g3d_busp",
1092+
CLK_CON_GAT_GOUT_G3D_BUSP_CLK, 21, 0, 0),
1093+
GATE(CLK_GOUT_G3D_SYSREG_PCLK, "gout_g3d_sysreg_pclk", "dout_g3d_busp",
1094+
CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, 21, 0, 0),
1095+
};
1096+
1097+
static const struct samsung_cmu_info g3d_cmu_info __initconst = {
1098+
.pll_clks = g3d_pll_clks,
1099+
.nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
1100+
.mux_clks = g3d_mux_clks,
1101+
.nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
1102+
.div_clks = g3d_div_clks,
1103+
.nr_div_clks = ARRAY_SIZE(g3d_div_clks),
1104+
.gate_clks = g3d_gate_clks,
1105+
.nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
1106+
.nr_clk_ids = G3D_NR_CLK,
1107+
.clk_regs = g3d_clk_regs,
1108+
.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
1109+
.clk_name = "dout_g3d_switch",
1110+
};
1111+
9951112
/* ---- CMU_HSI ------------------------------------------------------------- */
9961113

9971114
/* Register Offset definitions for CMU_HSI (0x13400000) */
@@ -1700,6 +1817,9 @@ static const struct of_device_id exynos850_cmu_of_match[] = {
17001817
}, {
17011818
.compatible = "samsung,exynos850-cmu-cmgp",
17021819
.data = &cmgp_cmu_info,
1820+
}, {
1821+
.compatible = "samsung,exynos850-cmu-g3d",
1822+
.data = &g3d_cmu_info,
17031823
}, {
17041824
.compatible = "samsung,exynos850-cmu-hsi",
17051825
.data = &hsi_cmu_info,

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