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Merge branch 'for-next/sysreg-gen' into for-next/core
* for-next/sysreg-gen: (32 commits) : Automatic system register definition generation. arm64/sysreg: Generate definitions for FAR_ELx arm64/sysreg: Generate definitions for DACR32_EL2 arm64/sysreg: Generate definitions for CSSELR_EL1 arm64/sysreg: Generate definitions for CPACR_ELx arm64/sysreg: Generate definitions for CONTEXTIDR_ELx arm64/sysreg: Generate definitions for CLIDR_EL1 arm64/sve: Generate ZCR definitions arm64/sme: Generate defintions for SVCR arm64/sme: Generate SMPRI_EL1 definitions arm64/sme: Automatically generate SMPRIMAP_EL2 definitions arm64/sme: Automatically generate SMIDR_EL1 defines arm64/sme: Automatically generate defines for SMCR arm64/sysreg: Support generation of RAZ fields arm64/sme: Remove _EL0 from name of SVCR - FIXME sysreg.h arm64/sme: Standardise bitfield names for SVCR arm64/sme: Drop SYS_ from SMIDR_EL1 defines arm64/fp: Rename SVE and SME LEN field name to _WIDTH arm64/fp: Make SVE and SME length register definition match architecture arm64/sysreg: fix odd line spacing arm64/sysreg: improve comment for regs without fields ...
2 parents 201729d + dffdead commit e003d53

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19 files changed

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lines changed

‎arch/arm64/include/asm/Kbuild

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,3 +7,4 @@ generic-y += parport.h
77
generic-y += user.h
88

99
generated-y += cpucaps.h
10+
generated-y += sysreg-defs.h

‎arch/arm64/include/asm/archrandom.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -142,7 +142,7 @@ static inline bool __init __early_cpu_has_rndr(void)
142142
{
143143
/* Open code as we run prior to the first call to cpufeature. */
144144
unsigned long ftr = read_sysreg_s(SYS_ID_AA64ISAR0_EL1);
145-
return (ftr >> ID_AA64ISAR0_RNDR_SHIFT) & 0xf;
145+
return (ftr >> ID_AA64ISAR0_EL1_RNDR_SHIFT) & 0xf;
146146
}
147147

148148
static inline bool __init __must_check

‎arch/arm64/include/asm/el2_setup.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -171,7 +171,7 @@
171171
msr_s SYS_SMCR_EL2, x1 // length for EL1.
172172

173173
mrs_s x1, SYS_SMIDR_EL1 // Priority mapping supported?
174-
ubfx x1, x1, #SYS_SMIDR_EL1_SMPS_SHIFT, #1
174+
ubfx x1, x1, #SMIDR_EL1_SMPS_SHIFT, #1
175175
cbz x1, .Lskip_sme_\@
176176

177177
msr_s SYS_SMPRIMAP_EL2, xzr // Make all priorities equal

‎arch/arm64/include/asm/fpsimd.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -67,12 +67,12 @@ extern void fpsimd_save_and_flush_cpu_state(void);
6767

6868
static inline bool thread_sm_enabled(struct thread_struct *thread)
6969
{
70-
return system_supports_sme() && (thread->svcr & SYS_SVCR_EL0_SM_MASK);
70+
return system_supports_sme() && (thread->svcr & SVCR_SM_MASK);
7171
}
7272

7373
static inline bool thread_za_enabled(struct thread_struct *thread)
7474
{
75-
return system_supports_sme() && (thread->svcr & SYS_SVCR_EL0_ZA_MASK);
75+
return system_supports_sme() && (thread->svcr & SVCR_ZA_MASK);
7676
}
7777

7878
/* Maximum VL that SVE/SME VL-agnostic software can transparently support */

‎arch/arm64/include/asm/processor.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -192,7 +192,7 @@ static inline unsigned int thread_get_sme_vl(struct thread_struct *thread)
192192

193193
static inline unsigned int thread_get_cur_vl(struct thread_struct *thread)
194194
{
195-
if (system_supports_sme() && (thread->svcr & SYS_SVCR_EL0_SM_MASK))
195+
if (system_supports_sme() && (thread->svcr & SVCR_SM_MASK))
196196
return thread_get_sme_vl(thread);
197197
else
198198
return thread_get_sve_vl(thread);

‎arch/arm64/include/asm/sysreg.h

Lines changed: 44 additions & 126 deletions
Original file line numberDiff line numberDiff line change
@@ -114,6 +114,14 @@
114114
#define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
115115
#define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
116116

117+
/*
118+
* Automatically generated definitions for system registers, the
119+
* manual encodings below are in the process of being converted to
120+
* come from here. The header relies on the definition of sys_reg()
121+
* earlier in this file.
122+
*/
123+
#include "asm/sysreg-defs.h"
124+
117125
/*
118126
* System registers, organised loosely by encoding but grouped together
119127
* where the architected name contains an index. e.g. ID_MMFR<n>_EL1.
@@ -193,27 +201,19 @@
193201
#define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4)
194202
#define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5)
195203

196-
#define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
197204
#define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
198205
#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2)
199206

200207
#define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
201208
#define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
202209
#define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
203210

204-
#define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0)
205211
#define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
206-
#define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2)
207212
#define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
208213
#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
209214

210-
#define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
211215
#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
212-
#define SYS_SMPRI_EL1 sys_reg(3, 0, 1, 2, 4)
213-
#define SYS_SMCR_EL1 sys_reg(3, 0, 1, 2, 6)
214216

215-
#define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
216-
#define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
217217
#define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
218218

219219
#define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
@@ -249,7 +249,6 @@
249249
#define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
250250
#define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
251251

252-
#define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0)
253252
#define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
254253

255254
#define SYS_PAR_EL1_F BIT(0)
@@ -403,8 +402,6 @@
403402
#define TRBIDR_ALIGN_MASK GENMASK(3, 0)
404403
#define TRBIDR_ALIGN_SHIFT 0
405404

406-
#define SMPRI_EL1_PRIORITY_MASK 0xf
407-
408405
#define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
409406
#define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
410407

@@ -450,35 +447,26 @@
450447
#define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
451448
#define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
452449

453-
#define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1)
454450
#define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4)
455451

456452
#define SYS_SCXTNUM_EL1 sys_reg(3, 0, 13, 0, 7)
457453

458454
#define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
459455

460456
#define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0)
461-
#define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1)
462457
#define SYS_GMID_EL1 sys_reg(3, 1, 0, 0, 4)
463-
#define SYS_SMIDR_EL1 sys_reg(3, 1, 0, 0, 6)
464458
#define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
465459

466-
#define SYS_SMIDR_EL1_IMPLEMENTER_SHIFT 24
467-
#define SYS_SMIDR_EL1_SMPS_SHIFT 15
468-
#define SYS_SMIDR_EL1_AFFINITY_SHIFT 0
469-
470-
#define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0)
460+
#define SMIDR_EL1_IMPLEMENTER_SHIFT 24
461+
#define SMIDR_EL1_SMPS_SHIFT 15
462+
#define SMIDR_EL1_AFFINITY_SHIFT 0
471463

472464
#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
473465
#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
474466

475467
#define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
476468
#define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
477469

478-
#define SYS_SVCR_EL0 sys_reg(3, 3, 4, 2, 2)
479-
#define SYS_SVCR_EL0_ZA_MASK 2
480-
#define SYS_SVCR_EL0_SM_MASK 1
481-
482470
#define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
483471
#define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
484472
#define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
@@ -563,12 +551,8 @@
563551
#define SYS_HFGRTR_EL2 sys_reg(3, 4, 1, 1, 4)
564552
#define SYS_HFGWTR_EL2 sys_reg(3, 4, 1, 1, 5)
565553
#define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6)
566-
#define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0)
567554
#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
568555
#define SYS_HCRX_EL2 sys_reg(3, 4, 1, 2, 2)
569-
#define SYS_SMPRIMAP_EL2 sys_reg(3, 4, 1, 2, 5)
570-
#define SYS_SMCR_EL2 sys_reg(3, 4, 1, 2, 6)
571-
#define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
572556
#define SYS_HDFGRTR_EL2 sys_reg(3, 4, 3, 1, 4)
573557
#define SYS_HDFGWTR_EL2 sys_reg(3, 4, 3, 1, 5)
574558
#define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
@@ -579,7 +563,6 @@
579563
#define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
580564
#define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
581565
#define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
582-
#define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
583566

584567
#define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
585568
#define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
@@ -625,9 +608,6 @@
625608

626609
/* VHE encodings for architectural EL0/1 system registers */
627610
#define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
628-
#define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
629-
#define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0)
630-
#define SYS_SMCR_EL12 sys_reg(3, 5, 1, 2, 6)
631611
#define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
632612
#define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
633613
#define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
@@ -637,11 +617,9 @@
637617
#define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
638618
#define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
639619
#define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
640-
#define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0)
641620
#define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
642621
#define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
643622
#define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
644-
#define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1)
645623
#define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
646624
#define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
647625
#define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
@@ -655,28 +633,26 @@
655633
#define SCTLR_ELx_DSSBS (BIT(44))
656634
#define SCTLR_ELx_ATA (BIT(43))
657635

658-
#define SCTLR_ELx_TCF_SHIFT 40
659-
#define SCTLR_ELx_TCF_NONE (UL(0x0) << SCTLR_ELx_TCF_SHIFT)
660-
#define SCTLR_ELx_TCF_SYNC (UL(0x1) << SCTLR_ELx_TCF_SHIFT)
661-
#define SCTLR_ELx_TCF_ASYNC (UL(0x2) << SCTLR_ELx_TCF_SHIFT)
662-
#define SCTLR_ELx_TCF_ASYMM (UL(0x3) << SCTLR_ELx_TCF_SHIFT)
663-
#define SCTLR_ELx_TCF_MASK (UL(0x3) << SCTLR_ELx_TCF_SHIFT)
664-
665636
#define SCTLR_ELx_ENIA_SHIFT 31
666637

667-
#define SCTLR_ELx_ITFSB (BIT(37))
668-
#define SCTLR_ELx_ENIA (BIT(SCTLR_ELx_ENIA_SHIFT))
669-
#define SCTLR_ELx_ENIB (BIT(30))
670-
#define SCTLR_ELx_ENDA (BIT(27))
671-
#define SCTLR_ELx_EE (BIT(25))
672-
#define SCTLR_ELx_IESB (BIT(21))
673-
#define SCTLR_ELx_WXN (BIT(19))
674-
#define SCTLR_ELx_ENDB (BIT(13))
675-
#define SCTLR_ELx_I (BIT(12))
676-
#define SCTLR_ELx_SA (BIT(3))
677-
#define SCTLR_ELx_C (BIT(2))
678-
#define SCTLR_ELx_A (BIT(1))
679-
#define SCTLR_ELx_M (BIT(0))
638+
#define SCTLR_ELx_ITFSB (BIT(37))
639+
#define SCTLR_ELx_ENIA (BIT(SCTLR_ELx_ENIA_SHIFT))
640+
#define SCTLR_ELx_ENIB (BIT(30))
641+
#define SCTLR_ELx_LSMAOE (BIT(29))
642+
#define SCTLR_ELx_nTLSMD (BIT(28))
643+
#define SCTLR_ELx_ENDA (BIT(27))
644+
#define SCTLR_ELx_EE (BIT(25))
645+
#define SCTLR_ELx_EIS (BIT(22))
646+
#define SCTLR_ELx_IESB (BIT(21))
647+
#define SCTLR_ELx_TSCXT (BIT(20))
648+
#define SCTLR_ELx_WXN (BIT(19))
649+
#define SCTLR_ELx_ENDB (BIT(13))
650+
#define SCTLR_ELx_I (BIT(12))
651+
#define SCTLR_ELx_EOS (BIT(11))
652+
#define SCTLR_ELx_SA (BIT(3))
653+
#define SCTLR_ELx_C (BIT(2))
654+
#define SCTLR_ELx_A (BIT(1))
655+
#define SCTLR_ELx_M (BIT(0))
680656

681657
/* SCTLR_EL2 specific flags. */
682658
#define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \
@@ -698,48 +674,24 @@
698674
(SCTLR_EL2_RES1 | ENDIAN_SET_EL2)
699675

700676
/* SCTLR_EL1 specific flags. */
701-
#define SCTLR_EL1_EPAN (BIT(57))
702-
#define SCTLR_EL1_ATA0 (BIT(42))
703-
704-
#define SCTLR_EL1_TCF0_SHIFT 38
705-
#define SCTLR_EL1_TCF0_NONE (UL(0x0) << SCTLR_EL1_TCF0_SHIFT)
706-
#define SCTLR_EL1_TCF0_SYNC (UL(0x1) << SCTLR_EL1_TCF0_SHIFT)
707-
#define SCTLR_EL1_TCF0_ASYNC (UL(0x2) << SCTLR_EL1_TCF0_SHIFT)
708-
#define SCTLR_EL1_TCF0_ASYMM (UL(0x3) << SCTLR_EL1_TCF0_SHIFT)
709-
#define SCTLR_EL1_TCF0_MASK (UL(0x3) << SCTLR_EL1_TCF0_SHIFT)
710-
711-
#define SCTLR_EL1_BT1 (BIT(36))
712-
#define SCTLR_EL1_BT0 (BIT(35))
713-
#define SCTLR_EL1_UCI (BIT(26))
714-
#define SCTLR_EL1_E0E (BIT(24))
715-
#define SCTLR_EL1_SPAN (BIT(23))
716-
#define SCTLR_EL1_NTWE (BIT(18))
717-
#define SCTLR_EL1_NTWI (BIT(16))
718-
#define SCTLR_EL1_UCT (BIT(15))
719-
#define SCTLR_EL1_DZE (BIT(14))
720-
#define SCTLR_EL1_UMA (BIT(9))
721-
#define SCTLR_EL1_SED (BIT(8))
722-
#define SCTLR_EL1_ITD (BIT(7))
723-
#define SCTLR_EL1_CP15BEN (BIT(5))
724-
#define SCTLR_EL1_SA0 (BIT(4))
725-
726-
#define SCTLR_EL1_RES1 ((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \
727-
(BIT(29)))
728-
729677
#ifdef CONFIG_CPU_BIG_ENDIAN
730678
#define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE)
731679
#else
732680
#define ENDIAN_SET_EL1 0
733681
#endif
734682

735683
#define INIT_SCTLR_EL1_MMU_OFF \
736-
(ENDIAN_SET_EL1 | SCTLR_EL1_RES1)
684+
(ENDIAN_SET_EL1 | SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | \
685+
SCTLR_EL1_EIS | SCTLR_EL1_TSCXT | SCTLR_EL1_EOS)
737686

738687
#define INIT_SCTLR_EL1_MMU_ON \
739-
(SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_EL1_SA0 | \
740-
SCTLR_EL1_SED | SCTLR_ELx_I | SCTLR_EL1_DZE | SCTLR_EL1_UCT | \
741-
SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \
742-
ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_EPAN | SCTLR_EL1_RES1)
688+
(SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | \
689+
SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I | \
690+
SCTLR_EL1_DZE | SCTLR_EL1_UCT | SCTLR_EL1_nTWE | \
691+
SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \
692+
ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_EPAN | \
693+
SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS | \
694+
SCTLR_EL1_TSCXT | SCTLR_EL1_EOS)
743695

744696
/* MAIR_ELx memory attributes (used by Linux) */
745697
#define MAIR_ATTR_DEVICE_nGnRnE UL(0x00)
@@ -752,25 +704,6 @@
752704
/* Position the attr at the correct index */
753705
#define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8))
754706

755-
/* id_aa64isar0 */
756-
#define ID_AA64ISAR0_RNDR_SHIFT 60
757-
#define ID_AA64ISAR0_TLB_SHIFT 56
758-
#define ID_AA64ISAR0_TS_SHIFT 52
759-
#define ID_AA64ISAR0_FHM_SHIFT 48
760-
#define ID_AA64ISAR0_DP_SHIFT 44
761-
#define ID_AA64ISAR0_SM4_SHIFT 40
762-
#define ID_AA64ISAR0_SM3_SHIFT 36
763-
#define ID_AA64ISAR0_SHA3_SHIFT 32
764-
#define ID_AA64ISAR0_RDM_SHIFT 28
765-
#define ID_AA64ISAR0_ATOMICS_SHIFT 20
766-
#define ID_AA64ISAR0_CRC32_SHIFT 16
767-
#define ID_AA64ISAR0_SHA2_SHIFT 12
768-
#define ID_AA64ISAR0_SHA1_SHIFT 8
769-
#define ID_AA64ISAR0_AES_SHIFT 4
770-
771-
#define ID_AA64ISAR0_TLB_RANGE_NI 0x0
772-
#define ID_AA64ISAR0_TLB_RANGE 0x2
773-
774707
/* id_aa64isar1 */
775708
#define ID_AA64ISAR1_I8MM_SHIFT 52
776709
#define ID_AA64ISAR1_DGH_SHIFT 48
@@ -1154,27 +1087,6 @@
11541087
#define DCZID_DZP_SHIFT 4
11551088
#define DCZID_BS_SHIFT 0
11561089

1157-
/*
1158-
* The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which
1159-
* are reserved by the SVE architecture for future expansion of the LEN
1160-
* field, with compatible semantics.
1161-
*/
1162-
#define ZCR_ELx_LEN_SHIFT 0
1163-
#define ZCR_ELx_LEN_SIZE 9
1164-
#define ZCR_ELx_LEN_MASK 0x1ff
1165-
1166-
#define SMCR_ELx_FA64_SHIFT 31
1167-
#define SMCR_ELx_FA64_MASK (1 << SMCR_ELx_FA64_SHIFT)
1168-
1169-
/*
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* The SMCR_ELx_LEN_* definitions intentionally include bits [8:4] which
1171-
* are reserved by the SME architecture for future expansion of the LEN
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* field, with compatible semantics.
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*/
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#define SMCR_ELx_LEN_SHIFT 0
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#define SMCR_ELx_LEN_SIZE 9
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#define SMCR_ELx_LEN_MASK 0x1ff
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11781090
#define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */
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#define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */
11801092

@@ -1412,4 +1324,10 @@
14121324

14131325
#endif
14141326

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#define SYS_FIELD_PREP(reg, field, val) \
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FIELD_PREP(reg##_##field##_MASK, val)
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#define SYS_FIELD_PREP_ENUM(reg, field, val) \
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FIELD_PREP(reg##_##field##_MASK, reg##_##field##_##val)
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#endif /* __ASM_SYSREG_H */

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