@@ -64,52 +64,29 @@ static void rockchip_pcie_clear_ep_ob_atu(struct rockchip_pcie *rockchip,
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}
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static void rockchip_pcie_prog_ep_ob_atu (struct rockchip_pcie * rockchip , u8 fn ,
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- u32 r , u32 type , u64 cpu_addr ,
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- u64 pci_addr , size_t size )
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+ u32 r , u64 cpu_addr , u64 pci_addr ,
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+ size_t size )
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{
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- u64 sz = 1ULL << fls64 (size - 1 );
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- int num_pass_bits = ilog2 (sz );
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- u32 addr0 , addr1 , desc0 , desc1 ;
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- bool is_nor_msg = (type == AXI_WRAPPER_NOR_MSG );
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+ int num_pass_bits = fls64 (size - 1 );
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+ u32 addr0 , addr1 , desc0 ;
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- /* The minimal region size is 1MB */
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if (num_pass_bits < 8 )
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num_pass_bits = 8 ;
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- cpu_addr -= rockchip -> mem_res -> start ;
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- addr0 = ((is_nor_msg ? 0x10 : (num_pass_bits - 1 )) &
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- PCIE_CORE_OB_REGION_ADDR0_NUM_BITS ) |
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- (lower_32_bits (cpu_addr ) & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR );
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- addr1 = upper_32_bits (is_nor_msg ? cpu_addr : pci_addr );
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- desc0 = ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN (fn ) | type ;
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- desc1 = 0 ;
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-
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- if (is_nor_msg ) {
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- rockchip_pcie_write (rockchip , 0 ,
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- ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0 (r ));
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- rockchip_pcie_write (rockchip , 0 ,
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- ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1 (r ));
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- rockchip_pcie_write (rockchip , desc0 ,
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- ROCKCHIP_PCIE_AT_OB_REGION_DESC0 (r ));
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- rockchip_pcie_write (rockchip , desc1 ,
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- ROCKCHIP_PCIE_AT_OB_REGION_DESC1 (r ));
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- } else {
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- /* PCI bus address region */
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- rockchip_pcie_write (rockchip , addr0 ,
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- ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0 (r ));
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- rockchip_pcie_write (rockchip , addr1 ,
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- ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1 (r ));
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- rockchip_pcie_write (rockchip , desc0 ,
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- ROCKCHIP_PCIE_AT_OB_REGION_DESC0 (r ));
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- rockchip_pcie_write (rockchip , desc1 ,
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- ROCKCHIP_PCIE_AT_OB_REGION_DESC1 (r ));
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-
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- addr0 =
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- ((num_pass_bits - 1 ) & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS ) |
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- (lower_32_bits (cpu_addr ) &
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- PCIE_CORE_OB_REGION_ADDR0_LO_ADDR );
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- addr1 = upper_32_bits (cpu_addr );
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- }
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+ addr0 = ((num_pass_bits - 1 ) & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS ) |
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+ (lower_32_bits (pci_addr ) & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR );
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+ addr1 = upper_32_bits (pci_addr );
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+ desc0 = ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN (fn ) | AXI_WRAPPER_MEM_WRITE ;
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+
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+ /* PCI bus address region */
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+ rockchip_pcie_write (rockchip , addr0 ,
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+ ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0 (r ));
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+ rockchip_pcie_write (rockchip , addr1 ,
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+ ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1 (r ));
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+ rockchip_pcie_write (rockchip , desc0 ,
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+ ROCKCHIP_PCIE_AT_OB_REGION_DESC0 (r ));
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+ rockchip_pcie_write (rockchip , 0 ,
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+ ROCKCHIP_PCIE_AT_OB_REGION_DESC1 (r ));
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}
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static int rockchip_pcie_ep_write_header (struct pci_epc * epc , u8 fn , u8 vfn ,
@@ -248,26 +225,20 @@ static void rockchip_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, u8 vfn,
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ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1 (fn , bar ));
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}
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+ static inline u32 rockchip_ob_region (phys_addr_t addr )
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+ {
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+ return (addr >> ilog2 (SZ_1M )) & 0x1f ;
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+ }
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+
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static int rockchip_pcie_ep_map_addr (struct pci_epc * epc , u8 fn , u8 vfn ,
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phys_addr_t addr , u64 pci_addr ,
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size_t size )
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{
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struct rockchip_pcie_ep * ep = epc_get_drvdata (epc );
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struct rockchip_pcie * pcie = & ep -> rockchip ;
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- u32 r ;
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+ u32 r = rockchip_ob_region ( addr ) ;
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- r = find_first_zero_bit (& ep -> ob_region_map , BITS_PER_LONG );
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- /*
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- * Region 0 is reserved for configuration space and shouldn't
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- * be used elsewhere per TRM, so leave it out.
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- */
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- if (r >= ep -> max_regions - 1 ) {
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- dev_err (& epc -> dev , "no free outbound region\n" );
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- return - EINVAL ;
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- }
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-
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- rockchip_pcie_prog_ep_ob_atu (pcie , fn , r , AXI_WRAPPER_MEM_WRITE , addr ,
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- pci_addr , size );
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+ rockchip_pcie_prog_ep_ob_atu (pcie , fn , r , addr , pci_addr , size );
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set_bit (r , & ep -> ob_region_map );
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ep -> ob_addr [r ] = addr ;
@@ -282,15 +253,11 @@ static void rockchip_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn, u8 vfn,
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struct rockchip_pcie * rockchip = & ep -> rockchip ;
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u32 r ;
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- for (r = 0 ; r < ep -> max_regions - 1 ; r ++ )
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+ for (r = 0 ; r < ep -> max_regions ; r ++ )
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if (ep -> ob_addr [r ] == addr )
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break ;
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- /*
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- * Region 0 is reserved for configuration space and shouldn't
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- * be used elsewhere per TRM, so leave it out.
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- */
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- if (r == ep -> max_regions - 1 )
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+ if (r == ep -> max_regions )
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return ;
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rockchip_pcie_clear_ep_ob_atu (rockchip , r );
@@ -387,7 +354,8 @@ static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn,
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struct rockchip_pcie * rockchip = & ep -> rockchip ;
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u16 flags , mme , data , data_mask ;
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u8 msi_count ;
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- u64 pci_addr , pci_addr_mask = 0xff ;
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+ u64 pci_addr ;
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+ u32 r ;
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/* Check MSI enable bit */
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flags = rockchip_pcie_read (& ep -> rockchip ,
@@ -421,21 +389,20 @@ static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn,
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ROCKCHIP_PCIE_EP_FUNC_BASE (fn ) +
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ROCKCHIP_PCIE_EP_MSI_CTRL_REG +
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PCI_MSI_ADDRESS_LO );
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- pci_addr &= GENMASK_ULL (63 , 2 );
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/* Set the outbound region if needed. */
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- if (unlikely (ep -> irq_pci_addr != (pci_addr & ~ pci_addr_mask ) ||
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+ if (unlikely (ep -> irq_pci_addr != (pci_addr & PCIE_ADDR_MASK ) ||
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ep -> irq_pci_fn != fn )) {
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- rockchip_pcie_prog_ep_ob_atu ( rockchip , fn , ep -> max_regions - 1 ,
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- AXI_WRAPPER_MEM_WRITE ,
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+ r = rockchip_ob_region ( ep -> irq_phys_addr );
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+ rockchip_pcie_prog_ep_ob_atu ( rockchip , fn , r ,
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ep -> irq_phys_addr ,
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- pci_addr & ~ pci_addr_mask ,
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- pci_addr_mask + 1 );
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- ep -> irq_pci_addr = (pci_addr & ~ pci_addr_mask );
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+ pci_addr & PCIE_ADDR_MASK ,
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+ ~ PCIE_ADDR_MASK + 1 );
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+ ep -> irq_pci_addr = (pci_addr & PCIE_ADDR_MASK );
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ep -> irq_pci_fn = fn ;
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}
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- writew (data , ep -> irq_cpu_addr + (pci_addr & pci_addr_mask ));
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+ writew (data , ep -> irq_cpu_addr + (pci_addr & ~ PCIE_ADDR_MASK ));
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return 0 ;
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}
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@@ -516,6 +483,8 @@ static int rockchip_pcie_parse_ep_dt(struct rockchip_pcie *rockchip,
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if (err < 0 || ep -> max_regions > MAX_REGION_LIMIT )
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ep -> max_regions = MAX_REGION_LIMIT ;
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+ ep -> ob_region_map = 0 ;
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+
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err = of_property_read_u8 (dev -> of_node , "max-functions" ,
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& ep -> epc -> max_functions );
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if (err < 0 )
@@ -536,7 +505,8 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev)
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struct rockchip_pcie * rockchip ;
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struct pci_epc * epc ;
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size_t max_regions ;
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- int err ;
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+ struct pci_epc_mem_window * windows = NULL ;
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+ int err , i ;
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ep = devm_kzalloc (dev , sizeof (* ep ), GFP_KERNEL );
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if (!ep )
@@ -583,15 +553,27 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev)
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/* Only enable function 0 by default */
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rockchip_pcie_write (rockchip , BIT (0 ), PCIE_CORE_PHY_FUNC_CFG );
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- err = pci_epc_mem_init (epc , rockchip -> mem_res -> start ,
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- resource_size (rockchip -> mem_res ), PAGE_SIZE );
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+ windows = devm_kcalloc (dev , ep -> max_regions ,
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+ sizeof (struct pci_epc_mem_window ), GFP_KERNEL );
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+ if (!windows ) {
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+ err = - ENOMEM ;
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+ goto err_uninit_port ;
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+ }
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+ for (i = 0 ; i < ep -> max_regions ; i ++ ) {
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+ windows [i ].phys_base = rockchip -> mem_res -> start + (SZ_1M * i );
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+ windows [i ].size = SZ_1M ;
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+ windows [i ].page_size = SZ_1M ;
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+ }
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+ err = pci_epc_multi_mem_init (epc , windows , ep -> max_regions );
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+ devm_kfree (dev , windows );
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+
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if (err < 0 ) {
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dev_err (dev , "failed to initialize the memory space\n" );
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goto err_uninit_port ;
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}
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ep -> irq_cpu_addr = pci_epc_mem_alloc_addr (epc , & ep -> irq_phys_addr ,
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- SZ_128K );
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+ SZ_1M );
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if (!ep -> irq_cpu_addr ) {
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dev_err (dev , "failed to reserve memory space for MSI\n" );
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err = - ENOMEM ;
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