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clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
PLL rate on RK356x is calculated through the simple formula: ((24000000 / _refdiv) * _fbdiv) / (_postdiv1 * _postdiv2) The PLL rate setting for 78.75MHz seems to be copied from 96MHz so this patch fixes it and configures it properly. Signed-off-by: Alibek Omarov <a1ba.omarov@gmail.com> Fixes: 842f4cb ("clk: rockchip: Add more PLL rates for rk3568") Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20230614134750.1056293-1-a1ba.omarov@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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drivers/clk/rockchip/clk-rk3568.c

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@@ -82,7 +82,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
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RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0),
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RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
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RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
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RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0),
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RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0),
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RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
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{ /* sentinel */ },
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};

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