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airliedairlied
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Merge tag 'amd-drm-fixes-6.4-2023-05-11' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amdgpu: - VCN3 fixes - APUs always support PCI atomics - Legacy power management fixes - DCN 3.1.4 fix - DCFCLK fix - Fix several RAS irq refcount mismatches - GPU Reset fix - GFX 11.0.4 fix Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230511141755.7896-1-alexander.deucher@amd.com
2 parents 9235c21 + 996e93a commit d8843ee

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14 files changed

+131
-71
lines changed

14 files changed

+131
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lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3757,6 +3757,12 @@ int amdgpu_device_init(struct amdgpu_device *adev,
37573757
adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *)
37583758
adev->virt.fw_reserve.p_pf2vf)->pcie_atomic_ops_support_flags ==
37593759
(PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCAP2_ATOMIC_COMP64);
3760+
/* APUs w/ gfx9 onwards doesn't reply on PCIe atomics, rather it is a
3761+
* internal path natively support atomics, set have_atomics_support to true.
3762+
*/
3763+
else if ((adev->flags & AMD_IS_APU) &&
3764+
(adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0)))
3765+
adev->have_atomics_support = true;
37603766
else
37613767
adev->have_atomics_support =
37623768
!pci_enable_atomic_ops_to_root(adev->pdev,
@@ -4506,7 +4512,11 @@ static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
45064512
dev_info(adev->dev, "recover vram bo from shadow start\n");
45074513
mutex_lock(&adev->shadow_list_lock);
45084514
list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) {
4509-
shadow = &vmbo->bo;
4515+
/* If vm is compute context or adev is APU, shadow will be NULL */
4516+
if (!vmbo->shadow)
4517+
continue;
4518+
shadow = vmbo->shadow;
4519+
45104520
/* No need to recover an evicted BO */
45114521
if (shadow->tbo.resource->mem_type != TTM_PL_TT ||
45124522
shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET ||

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -687,9 +687,11 @@ int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *r
687687
if (r)
688688
return r;
689689

690-
r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
691-
if (r)
692-
goto late_fini;
690+
if (adev->gfx.cp_ecc_error_irq.funcs) {
691+
r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
692+
if (r)
693+
goto late_fini;
694+
}
693695
} else {
694696
amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
695697
}

‎drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

Lines changed: 0 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -1315,13 +1315,6 @@ static int gfx_v11_0_sw_init(void *handle)
13151315
if (r)
13161316
return r;
13171317

1318-
/* ECC error */
1319-
r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1320-
GFX_11_0_0__SRCID__CP_ECC_ERROR,
1321-
&adev->gfx.cp_ecc_error_irq);
1322-
if (r)
1323-
return r;
1324-
13251318
/* FED error */
13261319
r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
13271320
GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT,
@@ -4444,7 +4437,6 @@ static int gfx_v11_0_hw_fini(void *handle)
44444437
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
44454438
int r;
44464439

4447-
amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);
44484440
amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
44494441
amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
44504442

@@ -5897,36 +5889,6 @@ static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev
58975889
}
58985890
}
58995891

5900-
#define CP_ME1_PIPE_INST_ADDR_INTERVAL 0x1
5901-
#define SET_ECC_ME_PIPE_STATE(reg_addr, state) \
5902-
do { \
5903-
uint32_t tmp = RREG32_SOC15_IP(GC, reg_addr); \
5904-
tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, state); \
5905-
WREG32_SOC15_IP(GC, reg_addr, tmp); \
5906-
} while (0)
5907-
5908-
static int gfx_v11_0_set_cp_ecc_error_state(struct amdgpu_device *adev,
5909-
struct amdgpu_irq_src *source,
5910-
unsigned type,
5911-
enum amdgpu_interrupt_state state)
5912-
{
5913-
uint32_t ecc_irq_state = 0;
5914-
uint32_t pipe0_int_cntl_addr = 0;
5915-
int i = 0;
5916-
5917-
ecc_irq_state = (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0;
5918-
5919-
pipe0_int_cntl_addr = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
5920-
5921-
WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, ecc_irq_state);
5922-
5923-
for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++)
5924-
SET_ECC_ME_PIPE_STATE(pipe0_int_cntl_addr + i * CP_ME1_PIPE_INST_ADDR_INTERVAL,
5925-
ecc_irq_state);
5926-
5927-
return 0;
5928-
}
5929-
59305892
static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev,
59315893
struct amdgpu_irq_src *src,
59325894
unsigned type,
@@ -6341,11 +6303,6 @@ static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = {
63416303
.process = gfx_v11_0_priv_inst_irq,
63426304
};
63436305

6344-
static const struct amdgpu_irq_src_funcs gfx_v11_0_cp_ecc_error_irq_funcs = {
6345-
.set = gfx_v11_0_set_cp_ecc_error_state,
6346-
.process = amdgpu_gfx_cp_ecc_error_irq,
6347-
};
6348-
63496306
static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = {
63506307
.process = gfx_v11_0_rlc_gc_fed_irq,
63516308
};
@@ -6361,9 +6318,6 @@ static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev)
63616318
adev->gfx.priv_inst_irq.num_types = 1;
63626319
adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs;
63636320

6364-
adev->gfx.cp_ecc_error_irq.num_types = 1; /* CP ECC error */
6365-
adev->gfx.cp_ecc_error_irq.funcs = &gfx_v11_0_cp_ecc_error_irq_funcs;
6366-
63676321
adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */
63686322
adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs;
63696323

‎drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3764,7 +3764,8 @@ static int gfx_v9_0_hw_fini(void *handle)
37643764
{
37653765
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
37663766

3767-
amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);
3767+
if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
3768+
amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);
37683769
amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
37693770
amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
37703771

‎drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -54,6 +54,7 @@ static int jpeg_v3_0_early_init(void *handle)
5454

5555
switch (adev->ip_versions[UVD_HWIP][0]) {
5656
case IP_VERSION(3, 1, 1):
57+
case IP_VERSION(3, 1, 2):
5758
break;
5859
default:
5960
harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);

‎drivers/gpu/drm/amd/amdgpu/nv.c

Lines changed: 16 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -98,6 +98,16 @@ static const struct amdgpu_video_codecs nv_video_codecs_decode =
9898
};
9999

100100
/* Sienna Cichlid */
101+
static const struct amdgpu_video_codec_info sc_video_codecs_encode_array[] = {
102+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)},
103+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)},
104+
};
105+
106+
static const struct amdgpu_video_codecs sc_video_codecs_encode = {
107+
.codec_count = ARRAY_SIZE(sc_video_codecs_encode_array),
108+
.codec_array = sc_video_codecs_encode_array,
109+
};
110+
101111
static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] =
102112
{
103113
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
@@ -136,8 +146,8 @@ static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 =
136146
/* SRIOV Sienna Cichlid, not const since data is controlled by host */
137147
static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] =
138148
{
139-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
140-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
149+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)},
150+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)},
141151
};
142152

143153
static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] =
@@ -237,12 +247,12 @@ static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
237247
} else {
238248
if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
239249
if (encode)
240-
*codecs = &nv_video_codecs_encode;
250+
*codecs = &sc_video_codecs_encode;
241251
else
242252
*codecs = &sc_video_codecs_decode_vcn1;
243253
} else {
244254
if (encode)
245-
*codecs = &nv_video_codecs_encode;
255+
*codecs = &sc_video_codecs_encode;
246256
else
247257
*codecs = &sc_video_codecs_decode_vcn0;
248258
}
@@ -251,14 +261,14 @@ static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
251261
case IP_VERSION(3, 0, 16):
252262
case IP_VERSION(3, 0, 2):
253263
if (encode)
254-
*codecs = &nv_video_codecs_encode;
264+
*codecs = &sc_video_codecs_encode;
255265
else
256266
*codecs = &sc_video_codecs_decode_vcn0;
257267
return 0;
258268
case IP_VERSION(3, 1, 1):
259269
case IP_VERSION(3, 1, 2):
260270
if (encode)
261-
*codecs = &nv_video_codecs_encode;
271+
*codecs = &sc_video_codecs_encode;
262272
else
263273
*codecs = &yc_video_codecs_decode;
264274
return 0;

‎drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1917,9 +1917,11 @@ static int sdma_v4_0_hw_fini(void *handle)
19171917
return 0;
19181918
}
19191919

1920-
for (i = 0; i < adev->sdma.num_instances; i++) {
1921-
amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
1922-
AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1920+
if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
1921+
for (i = 0; i < adev->sdma.num_instances; i++) {
1922+
amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
1923+
AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1924+
}
19231925
}
19241926

19251927
sdma_v4_0_ctx_switch_enable(adev, false);

‎drivers/gpu/drm/amd/amdgpu/soc21.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -711,7 +711,7 @@ static int soc21_common_early_init(void *handle)
711711
AMD_PG_SUPPORT_VCN_DPG |
712712
AMD_PG_SUPPORT_GFX_PG |
713713
AMD_PG_SUPPORT_JPEG;
714-
adev->external_rev_id = adev->rev_id + 0x1;
714+
adev->external_rev_id = adev->rev_id + 0x80;
715715
break;
716716

717717
default:

‎drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c

Lines changed: 65 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -423,3 +423,68 @@ void dcn314_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool
423423

424424
PERF_TRACE();
425425
}
426+
static void apply_symclk_on_tx_off_wa(struct dc_link *link)
427+
{
428+
/* There are use cases where SYMCLK is referenced by OTG. For instance
429+
* for TMDS signal, OTG relies SYMCLK even if TX video output is off.
430+
* However current link interface will power off PHY when disabling link
431+
* output. This will turn off SYMCLK generated by PHY. The workaround is
432+
* to identify such case where SYMCLK is still in use by OTG when we
433+
* power off PHY. When this is detected, we will temporarily power PHY
434+
* back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling
435+
* program_pix_clk interface. When OTG is disabled, we will then power
436+
* off PHY by calling disable link output again.
437+
*
438+
* In future dcn generations, we plan to rework transmitter control
439+
* interface so that we could have an option to set SYMCLK ON TX OFF
440+
* state in one step without this workaround
441+
*/
442+
443+
struct dc *dc = link->ctx->dc;
444+
struct pipe_ctx *pipe_ctx = NULL;
445+
uint8_t i;
446+
447+
if (link->phy_state.symclk_ref_cnts.otg > 0) {
448+
for (i = 0; i < MAX_PIPES; i++) {
449+
pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
450+
if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) {
451+
pipe_ctx->clock_source->funcs->program_pix_clk(
452+
pipe_ctx->clock_source,
453+
&pipe_ctx->stream_res.pix_clk_params,
454+
dc->link_srv->dp_get_encoding_format(
455+
&pipe_ctx->link_config.dp_link_settings),
456+
&pipe_ctx->pll_settings);
457+
link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
458+
break;
459+
}
460+
}
461+
}
462+
}
463+
464+
void dcn314_disable_link_output(struct dc_link *link,
465+
const struct link_resource *link_res,
466+
enum signal_type signal)
467+
{
468+
struct dc *dc = link->ctx->dc;
469+
const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
470+
struct dmcu *dmcu = dc->res_pool->dmcu;
471+
472+
if (signal == SIGNAL_TYPE_EDP &&
473+
link->dc->hwss.edp_backlight_control)
474+
link->dc->hwss.edp_backlight_control(link, false);
475+
else if (dmcu != NULL && dmcu->funcs->lock_phy)
476+
dmcu->funcs->lock_phy(dmcu);
477+
478+
link_hwss->disable_link_output(link, link_res, signal);
479+
link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
480+
/*
481+
* Add the logic to extract BOTH power up and power down sequences
482+
* from enable/disable link output and only call edp panel control
483+
* in enable_link_dp and disable_link_dp once.
484+
*/
485+
if (dmcu != NULL && dmcu->funcs->lock_phy)
486+
dmcu->funcs->unlock_phy(dmcu);
487+
dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
488+
489+
apply_symclk_on_tx_off_wa(link);
490+
}

‎drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,4 +45,6 @@ void dcn314_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool
4545

4646
void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);
4747

48+
void dcn314_disable_link_output(struct dc_link *link, const struct link_resource *link_res, enum signal_type signal);
49+
4850
#endif /* __DC_HWSS_DCN314_H__ */

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