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x86/sev: Dump SEV_STATUS
It is, and will be even more useful in the future, to dump the SEV features enabled according to SEV_STATUS. Do so: [ 0.542753] Memory Encryption Features active: AMD SEV SEV-ES SEV-SNP [ 0.544425] SEV: Status: SEV SEV-ES SEV-SNP DebugSwap Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Nikunj A Dadhania <nikunj@amd.com> Link: https://lore.kernel.org/r/20240219094216.GAZdMieDHKiI8aaP3n@fat_crate.local
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‎arch/x86/boot/compressed/sev.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -369,7 +369,7 @@ static void enforce_vmpl0(void)
369369
MSR_AMD64_SNP_VMPL_SSS | \
370370
MSR_AMD64_SNP_SECURE_TSC | \
371371
MSR_AMD64_SNP_VMGEXIT_PARAM | \
372-
MSR_AMD64_SNP_VMSA_REG_PROTECTION | \
372+
MSR_AMD64_SNP_VMSA_REG_PROT | \
373373
MSR_AMD64_SNP_RESERVED_BIT13 | \
374374
MSR_AMD64_SNP_RESERVED_BIT15 | \
375375
MSR_AMD64_SNP_RESERVED_MASK)

‎arch/x86/include/asm/msr-index.h

Lines changed: 35 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -594,36 +594,47 @@
594594
#define MSR_AMD64_SEV_ES_GHCB 0xc0010130
595595
#define MSR_AMD64_SEV 0xc0010131
596596
#define MSR_AMD64_SEV_ENABLED_BIT 0
597-
#define MSR_AMD64_SEV_ES_ENABLED_BIT 1
598-
#define MSR_AMD64_SEV_SNP_ENABLED_BIT 2
599597
#define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT)
598+
#define MSR_AMD64_SEV_ES_ENABLED_BIT 1
600599
#define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT)
600+
#define MSR_AMD64_SEV_SNP_ENABLED_BIT 2
601601
#define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT)
602-
#define MSR_AMD64_RMP_BASE 0xc0010132
603-
#define MSR_AMD64_RMP_END 0xc0010133
604-
605-
/* SNP feature bits enabled by the hypervisor */
606-
#define MSR_AMD64_SNP_VTOM BIT_ULL(3)
607-
#define MSR_AMD64_SNP_REFLECT_VC BIT_ULL(4)
608-
#define MSR_AMD64_SNP_RESTRICTED_INJ BIT_ULL(5)
609-
#define MSR_AMD64_SNP_ALT_INJ BIT_ULL(6)
610-
#define MSR_AMD64_SNP_DEBUG_SWAP BIT_ULL(7)
611-
#define MSR_AMD64_SNP_PREVENT_HOST_IBS BIT_ULL(8)
612-
#define MSR_AMD64_SNP_BTB_ISOLATION BIT_ULL(9)
613-
#define MSR_AMD64_SNP_VMPL_SSS BIT_ULL(10)
614-
#define MSR_AMD64_SNP_SECURE_TSC BIT_ULL(11)
615-
#define MSR_AMD64_SNP_VMGEXIT_PARAM BIT_ULL(12)
616-
#define MSR_AMD64_SNP_IBS_VIRT BIT_ULL(14)
617-
#define MSR_AMD64_SNP_VMSA_REG_PROTECTION BIT_ULL(16)
618-
#define MSR_AMD64_SNP_SMT_PROTECTION BIT_ULL(17)
619-
620-
/* SNP feature bits reserved for future use. */
621-
#define MSR_AMD64_SNP_RESERVED_BIT13 BIT_ULL(13)
622-
#define MSR_AMD64_SNP_RESERVED_BIT15 BIT_ULL(15)
623-
#define MSR_AMD64_SNP_RESERVED_MASK GENMASK_ULL(63, 18)
602+
#define MSR_AMD64_SNP_VTOM_BIT 3
603+
#define MSR_AMD64_SNP_VTOM BIT_ULL(MSR_AMD64_SNP_VTOM_BIT)
604+
#define MSR_AMD64_SNP_REFLECT_VC_BIT 4
605+
#define MSR_AMD64_SNP_REFLECT_VC BIT_ULL(MSR_AMD64_SNP_REFLECT_VC_BIT)
606+
#define MSR_AMD64_SNP_RESTRICTED_INJ_BIT 5
607+
#define MSR_AMD64_SNP_RESTRICTED_INJ BIT_ULL(MSR_AMD64_SNP_RESTRICTED_INJ_BIT)
608+
#define MSR_AMD64_SNP_ALT_INJ_BIT 6
609+
#define MSR_AMD64_SNP_ALT_INJ BIT_ULL(MSR_AMD64_SNP_ALT_INJ_BIT)
610+
#define MSR_AMD64_SNP_DEBUG_SWAP_BIT 7
611+
#define MSR_AMD64_SNP_DEBUG_SWAP BIT_ULL(MSR_AMD64_SNP_DEBUG_SWAP_BIT)
612+
#define MSR_AMD64_SNP_PREVENT_HOST_IBS_BIT 8
613+
#define MSR_AMD64_SNP_PREVENT_HOST_IBS BIT_ULL(MSR_AMD64_SNP_PREVENT_HOST_IBS_BIT)
614+
#define MSR_AMD64_SNP_BTB_ISOLATION_BIT 9
615+
#define MSR_AMD64_SNP_BTB_ISOLATION BIT_ULL(MSR_AMD64_SNP_BTB_ISOLATION_BIT)
616+
#define MSR_AMD64_SNP_VMPL_SSS_BIT 10
617+
#define MSR_AMD64_SNP_VMPL_SSS BIT_ULL(MSR_AMD64_SNP_VMPL_SSS_BIT)
618+
#define MSR_AMD64_SNP_SECURE_TSC_BIT 11
619+
#define MSR_AMD64_SNP_SECURE_TSC BIT_ULL(MSR_AMD64_SNP_SECURE_TSC_BIT)
620+
#define MSR_AMD64_SNP_VMGEXIT_PARAM_BIT 12
621+
#define MSR_AMD64_SNP_VMGEXIT_PARAM BIT_ULL(MSR_AMD64_SNP_VMGEXIT_PARAM_BIT)
622+
#define MSR_AMD64_SNP_RESERVED_BIT13 BIT_ULL(13)
623+
#define MSR_AMD64_SNP_IBS_VIRT_BIT 14
624+
#define MSR_AMD64_SNP_IBS_VIRT BIT_ULL(MSR_AMD64_SNP_IBS_VIRT_BIT)
625+
#define MSR_AMD64_SNP_RESERVED_BIT15 BIT_ULL(15)
626+
#define MSR_AMD64_SNP_VMSA_REG_PROT_BIT 16
627+
#define MSR_AMD64_SNP_VMSA_REG_PROT BIT_ULL(MSR_AMD64_SNP_VMSA_REG_PROT_BIT)
628+
#define MSR_AMD64_SNP_SMT_PROT_BIT 17
629+
#define MSR_AMD64_SNP_SMT_PROT BIT_ULL(MSR_AMD64_SNP_SMT_PROT_BIT)
630+
#define MSR_AMD64_SNP_RESV_BIT 18
631+
#define MSR_AMD64_SNP_RESERVED_MASK GENMASK_ULL(63, MSR_AMD64_SNP_RESV_BIT)
624632

625633
#define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f
626634

635+
#define MSR_AMD64_RMP_BASE 0xc0010132
636+
#define MSR_AMD64_RMP_END 0xc0010133
637+
627638
/* AMD Collaborative Processor Performance Control MSRs */
628639
#define MSR_AMD_CPPC_CAP1 0xc00102b0
629640
#define MSR_AMD_CPPC_ENABLE 0xc00102b1

‎arch/x86/include/asm/sev.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -228,6 +228,7 @@ void snp_accept_memory(phys_addr_t start, phys_addr_t end);
228228
u64 snp_get_unsupported_features(u64 status);
229229
u64 sev_get_status(void);
230230
void kdump_sev_callback(void);
231+
void sev_show_status(void);
231232
#else
232233
static inline void sev_es_ist_enter(struct pt_regs *regs) { }
233234
static inline void sev_es_ist_exit(void) { }
@@ -257,6 +258,7 @@ static inline void snp_accept_memory(phys_addr_t start, phys_addr_t end) { }
257258
static inline u64 snp_get_unsupported_features(u64 status) { return 0; }
258259
static inline u64 sev_get_status(void) { return 0; }
259260
static inline void kdump_sev_callback(void) { }
261+
static inline void sev_show_status(void) { }
260262
#endif
261263

262264
#ifdef CONFIG_KVM_AMD_SEV

‎arch/x86/kernel/sev.c

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,25 @@
5959
#define AP_INIT_CR0_DEFAULT 0x60000010
6060
#define AP_INIT_MXCSR_DEFAULT 0x1f80
6161

62+
static const char * const sev_status_feat_names[] = {
63+
[MSR_AMD64_SEV_ENABLED_BIT] = "SEV",
64+
[MSR_AMD64_SEV_ES_ENABLED_BIT] = "SEV-ES",
65+
[MSR_AMD64_SEV_SNP_ENABLED_BIT] = "SEV-SNP",
66+
[MSR_AMD64_SNP_VTOM_BIT] = "vTom",
67+
[MSR_AMD64_SNP_REFLECT_VC_BIT] = "ReflectVC",
68+
[MSR_AMD64_SNP_RESTRICTED_INJ_BIT] = "RI",
69+
[MSR_AMD64_SNP_ALT_INJ_BIT] = "AI",
70+
[MSR_AMD64_SNP_DEBUG_SWAP_BIT] = "DebugSwap",
71+
[MSR_AMD64_SNP_PREVENT_HOST_IBS_BIT] = "NoHostIBS",
72+
[MSR_AMD64_SNP_BTB_ISOLATION_BIT] = "BTBIsol",
73+
[MSR_AMD64_SNP_VMPL_SSS_BIT] = "VmplSSS",
74+
[MSR_AMD64_SNP_SECURE_TSC_BIT] = "SecureTSC",
75+
[MSR_AMD64_SNP_VMGEXIT_PARAM_BIT] = "VMGExitParam",
76+
[MSR_AMD64_SNP_IBS_VIRT_BIT] = "IBSVirt",
77+
[MSR_AMD64_SNP_VMSA_REG_PROT_BIT] = "VMSARegProt",
78+
[MSR_AMD64_SNP_SMT_PROT_BIT] = "SMTProt",
79+
};
80+
6281
/* For early boot hypervisor communication in SEV-ES enabled guests */
6382
static struct ghcb boot_ghcb_page __bss_decrypted __aligned(PAGE_SIZE);
6483

@@ -2275,3 +2294,19 @@ void kdump_sev_callback(void)
22752294
if (cpu_feature_enabled(X86_FEATURE_SEV_SNP))
22762295
wbinvd();
22772296
}
2297+
2298+
void sev_show_status(void)
2299+
{
2300+
int i;
2301+
2302+
pr_info("Status: ");
2303+
for (i = 0; i < MSR_AMD64_SNP_RESV_BIT; i++) {
2304+
if (sev_status & BIT_ULL(i)) {
2305+
if (!sev_status_feat_names[i])
2306+
continue;
2307+
2308+
pr_cont("%s ", sev_status_feat_names[i]);
2309+
}
2310+
}
2311+
pr_cont("\n");
2312+
}

‎arch/x86/mm/mem_encrypt.c

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,8 @@
1414
#include <linux/mem_encrypt.h>
1515
#include <linux/virtio_anchor.h>
1616

17+
#include <asm/sev.h>
18+
1719
/* Override for DMA direct allocation check - ARCH_HAS_FORCE_DMA_UNENCRYPTED */
1820
bool force_dma_unencrypted(struct device *dev)
1921
{
@@ -74,6 +76,9 @@ static void print_mem_encrypt_feature_info(void)
7476
pr_cont(" SEV-SNP");
7577

7678
pr_cont("\n");
79+
80+
sev_show_status();
81+
7782
break;
7883
default:
7984
pr_cont("Unknown\n");

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