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Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm
Pull ARM updates from Russell King: - amba bus updates - simplify ldr_this_cpu assembler macro for uniprocessor builds - avoid explicit assembler literal loads - more spectre-bhb improvements - add Cortex-A9 Errata 764319 workaround - add all unwind tables for modules * tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: ARM: 9204/2: module: Add all unwind tables when load module ARM: 9206/1: A9: Add ARM ERRATA 764319 workaround (Updated) ARM: 9201/1: spectre-bhb: rely on linker to emit cross-section literal loads ARM: 9200/1: spectre-bhb: avoid cross-subsection jump using a numbered label ARM: 9199/1: spectre-bhb: use local DSB and elide ISB in loop8 sequence ARM: 9198/1: spectre-bhb: simplify BPIALL vector macro ARM: 9195/1: entry: avoid explicit literal loads ARM: 9194/1: assembler: simplify ldr_this_cpu for !SMP builds ARM: 9192/1: amba: fix memory leak in amba_device_try_add() ARM: 9193/1: amba: Add amba_read_periphid() helper
2 parents 95fbef1 + b6f21d1 commit d6edf95

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lines changed

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arch/arm/Kconfig

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -972,6 +972,17 @@ config ARM_ERRATA_764369
972972
relevant cache maintenance functions and sets a specific bit
973973
in the diagnostic control register of the SCU.
974974

975+
config ARM_ERRATA_764319
976+
bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction"
977+
depends on CPU_V7
978+
help
979+
This option enables the workaround for the 764319 Cortex A-9 erratum.
980+
CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an
981+
unexpected Undefined Instruction exception when the DBGSWENABLE
982+
external pin is set to 0, even when the CP14 accesses are performed
983+
from a privileged mode. This work around catches the exception in a
984+
way the kernel does not stop execution.
985+
975986
config ARM_ERRATA_775420
976987
bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
977988
depends on CPU_V7

arch/arm/include/asm/assembler.h

Lines changed: 17 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -666,12 +666,11 @@ THUMB( orr \reg , \reg , #PSR_T_BIT )
666666
__adldst_l str, \src, \sym, \tmp, \cond
667667
.endm
668668

669-
.macro __ldst_va, op, reg, tmp, sym, cond
669+
.macro __ldst_va, op, reg, tmp, sym, cond, offset
670670
#if __LINUX_ARM_ARCH__ >= 7 || \
671671
!defined(CONFIG_ARM_HAS_GROUP_RELOCS) || \
672672
(defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS))
673673
mov_l \tmp, \sym, \cond
674-
\op\cond \reg, [\tmp]
675674
#else
676675
/*
677676
* Avoid a literal load, by emitting a sequence of ADD/LDR instructions
@@ -683,24 +682,29 @@ THUMB( orr \reg , \reg , #PSR_T_BIT )
683682
.reloc .L0_\@, R_ARM_ALU_PC_G0_NC, \sym
684683
.reloc .L1_\@, R_ARM_ALU_PC_G1_NC, \sym
685684
.reloc .L2_\@, R_ARM_LDR_PC_G2, \sym
686-
.L0_\@: sub\cond \tmp, pc, #8
687-
.L1_\@: sub\cond \tmp, \tmp, #4
688-
.L2_\@: \op\cond \reg, [\tmp, #0]
685+
.L0_\@: sub\cond \tmp, pc, #8 - \offset
686+
.L1_\@: sub\cond \tmp, \tmp, #4 - \offset
687+
.L2_\@:
689688
#endif
689+
\op\cond \reg, [\tmp, #\offset]
690690
.endm
691691

692692
/*
693693
* ldr_va - load a 32-bit word from the virtual address of \sym
694694
*/
695-
.macro ldr_va, rd:req, sym:req, cond
696-
__ldst_va ldr, \rd, \rd, \sym, \cond
695+
.macro ldr_va, rd:req, sym:req, cond, tmp, offset=0
696+
.ifnb \tmp
697+
__ldst_va ldr, \rd, \tmp, \sym, \cond, \offset
698+
.else
699+
__ldst_va ldr, \rd, \rd, \sym, \cond, \offset
700+
.endif
697701
.endm
698702

699703
/*
700704
* str_va - store a 32-bit word to the virtual address of \sym
701705
*/
702706
.macro str_va, rn:req, sym:req, tmp:req, cond
703-
__ldst_va str, \rn, \tmp, \sym, \cond
707+
__ldst_va str, \rn, \tmp, \sym, \cond, 0
704708
.endm
705709

706710
/*
@@ -727,9 +731,11 @@ THUMB( orr \reg , \reg , #PSR_T_BIT )
727731
* are permitted to overlap with 'rd' if != sp
728732
*/
729733
.macro ldr_this_cpu, rd:req, sym:req, t1:req, t2:req
730-
#if __LINUX_ARM_ARCH__ >= 7 || \
731-
!defined(CONFIG_ARM_HAS_GROUP_RELOCS) || \
732-
(defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS))
734+
#ifndef CONFIG_SMP
735+
ldr_va \rd, \sym, tmp=\t1
736+
#elif __LINUX_ARM_ARCH__ >= 7 || \
737+
!defined(CONFIG_ARM_HAS_GROUP_RELOCS) || \
738+
(defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS))
733739
this_cpu_offset \t1
734740
mov_l \t2, \sym
735741
ldr \rd, [\t1, \t2]

arch/arm/include/asm/module.h

Lines changed: 4 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -3,20 +3,10 @@
33
#define _ASM_ARM_MODULE_H
44

55
#include <asm-generic/module.h>
6-
7-
struct unwind_table;
6+
#include <asm/unwind.h>
87

98
#ifdef CONFIG_ARM_UNWIND
10-
enum {
11-
ARM_SEC_INIT,
12-
ARM_SEC_DEVINIT,
13-
ARM_SEC_CORE,
14-
ARM_SEC_EXIT,
15-
ARM_SEC_DEVEXIT,
16-
ARM_SEC_HOT,
17-
ARM_SEC_UNLIKELY,
18-
ARM_SEC_MAX,
19-
};
9+
#define ELF_SECTION_UNWIND 0x70000001
2010
#endif
2111

2212
#define PLT_ENT_STRIDE L1_CACHE_BYTES
@@ -36,7 +26,8 @@ struct mod_plt_sec {
3626

3727
struct mod_arch_specific {
3828
#ifdef CONFIG_ARM_UNWIND
39-
struct unwind_table *unwind[ARM_SEC_MAX];
29+
struct list_head unwind_list;
30+
struct unwind_table *init_table;
4031
#endif
4132
#ifdef CONFIG_ARM_MODULE_PLTS
4233
struct mod_plt_sec core;

arch/arm/include/asm/unwind.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@ struct unwind_idx {
2424

2525
struct unwind_table {
2626
struct list_head list;
27+
struct list_head mod_list;
2728
const struct unwind_idx *start;
2829
const struct unwind_idx *origin;
2930
const struct unwind_idx *stop;

arch/arm/kernel/entry-armv.S

Lines changed: 33 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -61,9 +61,8 @@
6161
.macro pabt_helper
6262
@ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5
6363
#ifdef MULTI_PABORT
64-
ldr ip, .LCprocfns
65-
mov lr, pc
66-
ldr pc, [ip, #PROCESSOR_PABT_FUNC]
64+
ldr_va ip, processor, offset=PROCESSOR_PABT_FUNC
65+
bl_r ip
6766
#else
6867
bl CPU_PABORT_HANDLER
6968
#endif
@@ -82,9 +81,8 @@
8281
@ the fault status register in r1. r9 must be preserved.
8382
@
8483
#ifdef MULTI_DABORT
85-
ldr ip, .LCprocfns
86-
mov lr, pc
87-
ldr pc, [ip, #PROCESSOR_DABT_FUNC]
84+
ldr_va ip, processor, offset=PROCESSOR_DABT_FUNC
85+
bl_r ip
8886
#else
8987
bl CPU_DABORT_HANDLER
9088
#endif
@@ -302,16 +300,6 @@ __fiq_svc:
302300
UNWIND(.fnend )
303301
ENDPROC(__fiq_svc)
304302

305-
.align 5
306-
.LCcralign:
307-
.word cr_alignment
308-
#ifdef MULTI_DABORT
309-
.LCprocfns:
310-
.word processor
311-
#endif
312-
.LCfp:
313-
.word fp_enter
314-
315303
/*
316304
* Abort mode handlers
317305
*/
@@ -370,7 +358,7 @@ ENDPROC(__fiq_abt)
370358
THUMB( stmia sp, {r0 - r12} )
371359

372360
ATRAP( mrc p15, 0, r7, c1, c0, 0)
373-
ATRAP( ldr r8, .LCcralign)
361+
ATRAP( ldr_va r8, cr_alignment)
374362

375363
ldmia r0, {r3 - r5}
376364
add r0, sp, #S_PC @ here for interlock avoidance
@@ -379,8 +367,6 @@ ENDPROC(__fiq_abt)
379367
str r3, [sp] @ save the "real" r0 copied
380368
@ from the exception stack
381369

382-
ATRAP( ldr r8, [r8, #0])
383-
384370
@
385371
@ We are now ready to fill in the remaining blanks on the stack:
386372
@
@@ -505,9 +491,7 @@ __und_usr_thumb:
505491
*/
506492
#if __LINUX_ARM_ARCH__ < 7
507493
/* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */
508-
#define NEED_CPU_ARCHITECTURE
509-
ldr r5, .LCcpu_architecture
510-
ldr r5, [r5]
494+
ldr_va r5, cpu_architecture
511495
cmp r5, #CPU_ARCH_ARMv7
512496
blo __und_usr_fault_16 @ 16bit undefined instruction
513497
/*
@@ -654,12 +638,6 @@ call_fpe:
654638
ret.w lr @ CP#14 (Debug)
655639
ret.w lr @ CP#15 (Control)
656640

657-
#ifdef NEED_CPU_ARCHITECTURE
658-
.align 2
659-
.LCcpu_architecture:
660-
.word __cpu_architecture
661-
#endif
662-
663641
#ifdef CONFIG_NEON
664642
.align 6
665643

@@ -685,9 +663,8 @@ call_fpe:
685663
#endif
686664

687665
do_fpe:
688-
ldr r4, .LCfp
689666
add r10, r10, #TI_FPSTATE @ r10 = workspace
690-
ldr pc, [r4] @ Call FP module USR entry point
667+
ldr_va pc, fp_enter, tmp=r4 @ Call FP module USR entry point
691668

692669
/*
693670
* The FP module is called with these registers set:
@@ -1101,6 +1078,12 @@ __kuser_helper_end:
11011078
*/
11021079
.macro vector_stub, name, mode, correction=0
11031080
.align 5
1081+
#ifdef CONFIG_HARDEN_BRANCH_HISTORY
1082+
vector_bhb_bpiall_\name:
1083+
mcr p15, 0, r0, c7, c5, 6 @ BPIALL
1084+
@ isb not needed due to "movs pc, lr" in the vector stub
1085+
@ which gives a "context synchronisation".
1086+
#endif
11041087

11051088
vector_\name:
11061089
.if \correction
@@ -1111,7 +1094,8 @@ vector_\name:
11111094
stmia sp, {r0, lr} @ save r0, lr
11121095

11131096
@ Save spsr_<exception> (parent CPSR)
1114-
2: mrs lr, spsr
1097+
.Lvec_\name:
1098+
mrs lr, spsr
11151099
str lr, [sp, #8] @ save spsr
11161100

11171101
@
@@ -1148,25 +1132,11 @@ vector_bhb_loop8_\name:
11481132
3: W(b) . + 4
11491133
subs r0, r0, #1
11501134
bne 3b
1151-
dsb
1152-
isb
1153-
b 2b
1154-
ENDPROC(vector_bhb_loop8_\name)
1155-
1156-
vector_bhb_bpiall_\name:
1157-
.if \correction
1158-
sub lr, lr, #\correction
1159-
.endif
1160-
1161-
@ Save r0, lr_<exception> (parent PC)
1162-
stmia sp, {r0, lr}
1163-
1164-
@ bhb workaround
1165-
mcr p15, 0, r0, c7, c5, 6 @ BPIALL
1135+
dsb nsh
11661136
@ isb not needed due to "movs pc, lr" in the vector stub
11671137
@ which gives a "context synchronisation".
1168-
b 2b
1169-
ENDPROC(vector_bhb_bpiall_\name)
1138+
b .Lvec_\name
1139+
ENDPROC(vector_bhb_loop8_\name)
11701140
.previous
11711141
#endif
11721142

@@ -1176,10 +1146,15 @@ ENDPROC(vector_bhb_bpiall_\name)
11761146
.endm
11771147

11781148
.section .stubs, "ax", %progbits
1179-
@ This must be the first word
1149+
@ These need to remain at the start of the section so that
1150+
@ they are in range of the 'SWI' entries in the vector tables
1151+
@ located 4k down.
1152+
.L__vector_swi:
11801153
.word vector_swi
11811154
#ifdef CONFIG_HARDEN_BRANCH_HISTORY
1155+
.L__vector_bhb_loop8_swi:
11821156
.word vector_bhb_loop8_swi
1157+
.L__vector_bhb_bpiall_swi:
11831158
.word vector_bhb_bpiall_swi
11841159
#endif
11851160

@@ -1322,10 +1297,11 @@ vector_addrexcptn:
13221297
.globl vector_fiq
13231298

13241299
.section .vectors, "ax", %progbits
1325-
.L__vectors_start:
13261300
W(b) vector_rst
13271301
W(b) vector_und
1328-
W(ldr) pc, .L__vectors_start + 0x1000
1302+
ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_swi )
1303+
THUMB( .reloc ., R_ARM_THM_PC12, .L__vector_swi )
1304+
W(ldr) pc, .
13291305
W(b) vector_pabt
13301306
W(b) vector_dabt
13311307
W(b) vector_addrexcptn
@@ -1334,21 +1310,23 @@ vector_addrexcptn:
13341310

13351311
#ifdef CONFIG_HARDEN_BRANCH_HISTORY
13361312
.section .vectors.bhb.loop8, "ax", %progbits
1337-
.L__vectors_bhb_loop8_start:
13381313
W(b) vector_rst
13391314
W(b) vector_bhb_loop8_und
1340-
W(ldr) pc, .L__vectors_bhb_loop8_start + 0x1004
1315+
ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_bhb_loop8_swi )
1316+
THUMB( .reloc ., R_ARM_THM_PC12, .L__vector_bhb_loop8_swi )
1317+
W(ldr) pc, .
13411318
W(b) vector_bhb_loop8_pabt
13421319
W(b) vector_bhb_loop8_dabt
13431320
W(b) vector_addrexcptn
13441321
W(b) vector_bhb_loop8_irq
13451322
W(b) vector_bhb_loop8_fiq
13461323

13471324
.section .vectors.bhb.bpiall, "ax", %progbits
1348-
.L__vectors_bhb_bpiall_start:
13491325
W(b) vector_rst
13501326
W(b) vector_bhb_bpiall_und
1351-
W(ldr) pc, .L__vectors_bhb_bpiall_start + 0x1008
1327+
ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_bhb_bpiall_swi )
1328+
THUMB( .reloc ., R_ARM_THM_PC12, .L__vector_bhb_bpiall_swi )
1329+
W(ldr) pc, .
13521330
W(b) vector_bhb_bpiall_pabt
13531331
W(b) vector_bhb_bpiall_dabt
13541332
W(b) vector_addrexcptn

arch/arm/kernel/entry-common.S

Lines changed: 2 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -164,7 +164,7 @@ ENTRY(vector_bhb_loop8_swi)
164164
1: b 2f
165165
2: subs r8, r8, #1
166166
bne 1b
167-
dsb
167+
dsb nsh
168168
isb
169169
b 3f
170170
ENDPROC(vector_bhb_loop8_swi)
@@ -198,7 +198,7 @@ ENTRY(vector_swi)
198198
#endif
199199
reload_current r10, ip
200200
zero_fp
201-
alignment_trap r10, ip, __cr_alignment
201+
alignment_trap r10, ip, cr_alignment
202202
asm_trace_hardirqs_on save=0
203203
enable_irq_notrace
204204
ct_user_exit save=0
@@ -328,14 +328,6 @@ __sys_trace_return:
328328
bl syscall_trace_exit
329329
b ret_slow_syscall
330330

331-
.align 5
332-
#ifdef CONFIG_ALIGNMENT_TRAP
333-
.type __cr_alignment, #object
334-
__cr_alignment:
335-
.word cr_alignment
336-
#endif
337-
.ltorg
338-
339331
.macro syscall_table_start, sym
340332
.equ __sys_nr, 0
341333
.type \sym, #object

arch/arm/kernel/entry-header.S

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -48,8 +48,7 @@
4848
.macro alignment_trap, rtmp1, rtmp2, label
4949
#ifdef CONFIG_ALIGNMENT_TRAP
5050
mrc p15, 0, \rtmp2, c1, c0, 0
51-
ldr \rtmp1, \label
52-
ldr \rtmp1, [\rtmp1]
51+
ldr_va \rtmp1, \label
5352
teq \rtmp1, \rtmp2
5453
mcrne p15, 0, \rtmp1, c1, c0, 0
5554
#endif

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