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cache: Add L2 cache management for Andes AX45MP RISC-V core
I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. The accesses from IOCP are coherent with D-Caches and L2 Cache. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC due to this reason IP blocks using DMA will fail. The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA) block that allows dynamic adjustment of memory attributes in the runtime. It contains a configurable amount of PMA entries implemented as CSR registers to control the attributes of memory locations in interest. Below are the memory attributes supported: * Device, Non-bufferable * Device, bufferable * Memory, Non-cacheable, Non-bufferable * Memory, Non-cacheable, Bufferable * Memory, Write-back, No-allocate * Memory, Write-back, Read-allocate * Memory, Write-back, Write-allocate * Memory, Write-back, Read and Write-allocate More info about PMA (section 10.3): Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf As a workaround for SoCs with IOCP disabled CMO needs to be handled by software. Firstly OpenSBI configures the memory region as "Memory, Non-cacheable, Bufferable" and passes this region as a global shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA allocations happen from this region and synchronization callbacks are implemented to synchronize when doing DMA transactions. Example PMA region passes as a DT node from OpenSBI: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; pma_resv0@58000000 { compatible = "shared-dma-pool"; reg = <0x0 0x58000000 0x0 0x08000000>; no-map; linux,dma-default; }; }; Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1 Link: https://lore.kernel.org/r/20230818135723.80612-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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MAINTAINERS

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@@ -20241,6 +20241,13 @@ S: Supported
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git
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F: drivers/staging/
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STANDALONE CACHE CONTROLLER DRIVERS
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M: Conor Dooley <conor@kernel.org>
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L: linux-riscv@lists.infradead.org
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S: Maintained
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T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
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F: drivers/cache
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STARFIRE/DURALAN NETWORK DRIVER
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M: Ion Badulescu <ionut@badula.org>
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S: Odd Fixes

drivers/Kconfig

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@@ -15,6 +15,8 @@ source "drivers/base/Kconfig"
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source "drivers/bus/Kconfig"
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source "drivers/cache/Kconfig"
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source "drivers/connector/Kconfig"
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source "drivers/firmware/Kconfig"

drivers/Makefile

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MAKEFLAGS += --include-dir=$(srctree)
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endif
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obj-y += cache/
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obj-y += irqchip/
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obj-y += bus/
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drivers/cache/Kconfig

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# SPDX-License-Identifier: GPL-2.0
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menu "Cache Drivers"
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config AX45MP_L2_CACHE
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bool "Andes Technology AX45MP L2 Cache controller"
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depends on RISCV_DMA_NONCOHERENT
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select RISCV_NONSTANDARD_CACHE_OPS
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help
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Support for the L2 cache controller on Andes Technology AX45MP platforms.
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endmenu

drivers/cache/Makefile

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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_AX45MP_L2_CACHE) += ax45mp_cache.o

drivers/cache/ax45mp_cache.c

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// SPDX-License-Identifier: GPL-2.0
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/*
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* non-coherent cache functions for Andes AX45MP
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*
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* Copyright (C) 2023 Renesas Electronics Corp.
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*/
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#include <linux/cacheflush.h>
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#include <linux/cacheinfo.h>
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#include <linux/dma-direction.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <asm/dma-noncoherent.h>
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/* L2 cache registers */
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#define AX45MP_L2C_REG_CTL_OFFSET 0x8
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#define AX45MP_L2C_REG_C0_CMD_OFFSET 0x40
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#define AX45MP_L2C_REG_C0_ACC_OFFSET 0x48
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#define AX45MP_L2C_REG_STATUS_OFFSET 0x80
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/* D-cache operation */
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#define AX45MP_CCTL_L1D_VA_INVAL 0 /* Invalidate an L1 cache entry */
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#define AX45MP_CCTL_L1D_VA_WB 1 /* Write-back an L1 cache entry */
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/* L2 CCTL status */
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#define AX45MP_CCTL_L2_STATUS_IDLE 0
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/* L2 CCTL status cores mask */
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#define AX45MP_CCTL_L2_STATUS_C0_MASK 0xf
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/* L2 cache operation */
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#define AX45MP_CCTL_L2_PA_INVAL 0x8 /* Invalidate an L2 cache entry */
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#define AX45MP_CCTL_L2_PA_WB 0x9 /* Write-back an L2 cache entry */
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#define AX45MP_L2C_REG_PER_CORE_OFFSET 0x10
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#define AX45MP_CCTL_L2_STATUS_PER_CORE_OFFSET 4
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#define AX45MP_L2C_REG_CN_CMD_OFFSET(n) \
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(AX45MP_L2C_REG_C0_CMD_OFFSET + ((n) * AX45MP_L2C_REG_PER_CORE_OFFSET))
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#define AX45MP_L2C_REG_CN_ACC_OFFSET(n) \
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(AX45MP_L2C_REG_C0_ACC_OFFSET + ((n) * AX45MP_L2C_REG_PER_CORE_OFFSET))
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#define AX45MP_CCTL_L2_STATUS_CN_MASK(n) \
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(AX45MP_CCTL_L2_STATUS_C0_MASK << ((n) * AX45MP_CCTL_L2_STATUS_PER_CORE_OFFSET))
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#define AX45MP_CCTL_REG_UCCTLBEGINADDR_NUM 0x80b
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#define AX45MP_CCTL_REG_UCCTLCOMMAND_NUM 0x80c
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#define AX45MP_CACHE_LINE_SIZE 64
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struct ax45mp_priv {
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void __iomem *l2c_base;
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u32 ax45mp_cache_line_size;
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};
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static struct ax45mp_priv ax45mp_priv;
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/* L2 Cache operations */
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static inline uint32_t ax45mp_cpu_l2c_get_cctl_status(void)
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{
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return readl(ax45mp_priv.l2c_base + AX45MP_L2C_REG_STATUS_OFFSET);
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}
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static void ax45mp_cpu_cache_operation(unsigned long start, unsigned long end,
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unsigned int l1_op, unsigned int l2_op)
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{
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unsigned long line_size = ax45mp_priv.ax45mp_cache_line_size;
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void __iomem *base = ax45mp_priv.l2c_base;
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int mhartid = smp_processor_id();
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unsigned long pa;
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while (end > start) {
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csr_write(AX45MP_CCTL_REG_UCCTLBEGINADDR_NUM, start);
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csr_write(AX45MP_CCTL_REG_UCCTLCOMMAND_NUM, l1_op);
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pa = virt_to_phys((void *)start);
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writel(pa, base + AX45MP_L2C_REG_CN_ACC_OFFSET(mhartid));
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writel(l2_op, base + AX45MP_L2C_REG_CN_CMD_OFFSET(mhartid));
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while ((ax45mp_cpu_l2c_get_cctl_status() &
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AX45MP_CCTL_L2_STATUS_CN_MASK(mhartid)) !=
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AX45MP_CCTL_L2_STATUS_IDLE)
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;
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start += line_size;
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}
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}
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/* Write-back L1 and L2 cache entry */
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static inline void ax45mp_cpu_dcache_wb_range(unsigned long start, unsigned long end)
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{
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ax45mp_cpu_cache_operation(start, end, AX45MP_CCTL_L1D_VA_WB,
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AX45MP_CCTL_L2_PA_WB);
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}
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/* Invalidate the L1 and L2 cache entry */
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static inline void ax45mp_cpu_dcache_inval_range(unsigned long start, unsigned long end)
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{
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ax45mp_cpu_cache_operation(start, end, AX45MP_CCTL_L1D_VA_INVAL,
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AX45MP_CCTL_L2_PA_INVAL);
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}
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static void ax45mp_dma_cache_inv(phys_addr_t paddr, size_t size)
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{
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unsigned long start = (unsigned long)phys_to_virt(paddr);
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unsigned long end = start + size;
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unsigned long line_size;
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unsigned long flags;
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if (unlikely(start == end))
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return;
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line_size = ax45mp_priv.ax45mp_cache_line_size;
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start = start & (~(line_size - 1));
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end = ((end + line_size - 1) & (~(line_size - 1)));
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local_irq_save(flags);
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ax45mp_cpu_dcache_inval_range(start, end);
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local_irq_restore(flags);
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}
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static void ax45mp_dma_cache_wback(phys_addr_t paddr, size_t size)
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{
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unsigned long start = (unsigned long)phys_to_virt(paddr);
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unsigned long end = start + size;
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unsigned long line_size;
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unsigned long flags;
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line_size = ax45mp_priv.ax45mp_cache_line_size;
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start = start & (~(line_size - 1));
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local_irq_save(flags);
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ax45mp_cpu_dcache_wb_range(start, end);
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local_irq_restore(flags);
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}
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static void ax45mp_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
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{
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ax45mp_dma_cache_wback(paddr, size);
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ax45mp_dma_cache_inv(paddr, size);
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}
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static int ax45mp_get_l2_line_size(struct device_node *np)
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{
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int ret;
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ret = of_property_read_u32(np, "cache-line-size", &ax45mp_priv.ax45mp_cache_line_size);
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if (ret) {
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pr_err("Failed to get cache-line-size, defaulting to 64 bytes\n");
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return ret;
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}
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if (ax45mp_priv.ax45mp_cache_line_size != AX45MP_CACHE_LINE_SIZE) {
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pr_err("Expected cache-line-size to be 64 bytes (found:%u)\n",
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ax45mp_priv.ax45mp_cache_line_size);
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return -EINVAL;
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}
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return 0;
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}
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static const struct riscv_nonstd_cache_ops ax45mp_cmo_ops __initdata = {
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.wback = &ax45mp_dma_cache_wback,
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.inv = &ax45mp_dma_cache_inv,
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.wback_inv = &ax45mp_dma_cache_wback_inv,
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};
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static const struct of_device_id ax45mp_cache_ids[] = {
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{ .compatible = "andestech,ax45mp-cache" },
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{ /* sentinel */ }
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};
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static int __init ax45mp_cache_init(void)
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{
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struct device_node *np;
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struct resource res;
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int ret;
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np = of_find_matching_node(NULL, ax45mp_cache_ids);
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if (!of_device_is_available(np))
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return -ENODEV;
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ret = of_address_to_resource(np, 0, &res);
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if (ret)
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return ret;
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/*
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* If IOCP is present on the Andes AX45MP core riscv_cbom_block_size
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* will be 0 for sure, so we can definitely rely on it. If
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* riscv_cbom_block_size = 0 we don't need to handle CMO using SW any
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* more so we just return success here and only if its being set we
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* continue further in the probe path.
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*/
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if (!riscv_cbom_block_size)
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return 0;
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ax45mp_priv.l2c_base = ioremap(res.start, resource_size(&res));
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if (!ax45mp_priv.l2c_base)
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return -ENOMEM;
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ret = ax45mp_get_l2_line_size(np);
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if (ret) {
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iounmap(ax45mp_priv.l2c_base);
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return ret;
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}
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riscv_noncoherent_register_cache_ops(&ax45mp_cmo_ops);
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return 0;
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}
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early_initcall(ax45mp_cache_init);

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