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xpardee-createjwrdegoede
xpardee-create
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platform/x86:intel/pmc: Add Meteor Lake IOE-M PMC related maps
Add device ID and register maps for the PMC in IO expansion die M in Meteor Lake. Signed-off-by: Xi Pardee <xi.pardee@intel.com> Signed-off-by: Rajvi Jingar <rajvi.jingar@linux.intel.com> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Link: https://lore.kernel.org/r/20230613225347.2720665-9-rajvi.jingar@linux.intel.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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‎drivers/platform/x86/intel/pmc/core.h

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@@ -478,6 +478,12 @@ extern const struct pmc_bit_map mtl_ioep_vnn_req_status_3_map[];
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extern const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[];
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extern const struct pmc_bit_map *mtl_ioep_lpm_maps[];
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extern const struct pmc_reg_map mtl_ioep_reg_map;
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extern const struct pmc_bit_map mtl_ioem_pfear_map[];
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extern const struct pmc_bit_map *ext_mtl_ioem_pfear_map[];
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extern const struct pmc_bit_map mtl_ioem_power_gating_status_1_map[];
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extern const struct pmc_bit_map mtl_ioem_vnn_req_status_1_map[];
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extern const struct pmc_bit_map *mtl_ioem_lpm_maps[];
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extern const struct pmc_reg_map mtl_ioem_reg_map;
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extern void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev);
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extern int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value);

‎drivers/platform/x86/intel/pmc/mtl.c

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@@ -784,8 +784,149 @@ const struct pmc_reg_map mtl_ioep_reg_map = {
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.ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,
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};
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const struct pmc_bit_map mtl_ioem_pfear_map[] = {
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{"PMC_0", BIT(0)},
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{"OPI", BIT(1)},
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{"TCSS", BIT(2)},
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{"RSVD3", BIT(3)},
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{"SPA", BIT(4)},
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{"SPB", BIT(5)},
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{"SPC", BIT(6)},
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{"IOE_D2D_3", BIT(7)},
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{"RSVD8", BIT(0)},
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{"RSVD9", BIT(1)},
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{"SPE", BIT(2)},
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{"RSVD11", BIT(3)},
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{"RSVD12", BIT(4)},
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{"SPD", BIT(5)},
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{"ACE_7", BIT(6)},
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{"RSVD15", BIT(7)},
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{"ACE_0", BIT(0)},
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{"FIACPCB_P", BIT(1)},
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{"P2S", BIT(2)},
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{"RSVD19", BIT(3)},
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{"ACE_8", BIT(4)},
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{"IOE_D2D_0", BIT(5)},
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{"FUSE", BIT(6)},
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{"RSVD23", BIT(7)},
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{"FIACPCB_P5", BIT(0)},
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{"ACE_3", BIT(1)},
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{"RSF5", BIT(2)},
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{"ACE_2", BIT(3)},
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{"ACE_4", BIT(4)},
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{"RSVD29", BIT(5)},
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{"RSF10", BIT(6)},
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{"MPFPW5", BIT(7)},
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{"PSF9", BIT(0)},
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{"MPFPW4", BIT(1)},
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{"RSVD34", BIT(2)},
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{"RSVD35", BIT(3)},
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{"RSVD36", BIT(4)},
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{"RSVD37", BIT(5)},
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{"RSVD38", BIT(6)},
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{"RSVD39", BIT(7)},
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{"SBR0", BIT(0)},
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{"SBR1", BIT(1)},
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{"SBR2", BIT(2)},
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{"SBR3", BIT(3)},
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{"SBR4", BIT(4)},
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{"RSVD45", BIT(5)},
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{"RSVD46", BIT(6)},
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{"RSVD47", BIT(7)},
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{"RSVD48", BIT(0)},
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{"FIA_P5", BIT(1)},
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{"RSVD50", BIT(2)},
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{"RSVD51", BIT(3)},
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{"RSVD52", BIT(4)},
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{"RSVD53", BIT(5)},
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{"RSVD54", BIT(6)},
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{"ACE_1", BIT(7)},
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{"RSVD56", BIT(0)},
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{"ACE_5", BIT(1)},
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{"RSVD58", BIT(2)},
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{"G5FPW1", BIT(3)},
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{"RSVD60", BIT(4)},
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{"ACE_6", BIT(5)},
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{"RSVD62", BIT(6)},
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{"GBETSN1", BIT(7)},
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{"RSVD64", BIT(0)},
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{"FIA", BIT(1)},
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{"RSVD66", BIT(2)},
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{"FIA_P", BIT(3)},
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{"TAM", BIT(4)},
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{"GBETSN", BIT(5)},
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{"IOE_D2D_2", BIT(6)},
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{"IOE_D2D_1", BIT(7)},
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{"SPF", BIT(0)},
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{"PMC_1", BIT(1)},
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{}
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};
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const struct pmc_bit_map *ext_mtl_ioem_pfear_map[] = {
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mtl_ioem_pfear_map,
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NULL
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};
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const struct pmc_bit_map mtl_ioem_power_gating_status_1_map[] = {
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{"PSF9_PGD0_PG_STS", BIT(0)},
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{"MPFPW4_PGD0_PG_STS", BIT(1)},
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{"SBR0_PGD0_PG_STS", BIT(8)},
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{"SBR1_PGD0_PG_STS", BIT(9)},
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{"SBR2_PGD0_PG_STS", BIT(10)},
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{"SBR3_PGD0_PG_STS", BIT(11)},
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{"SBR4_PGD0_PG_STS", BIT(12)},
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{"FIA_P5_PGD0_PG_STS", BIT(17)},
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{"ACE_PGD1_PGD0_PG_STS", BIT(23)},
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{"ACE_PGD5_PGD1_PG_STS", BIT(25)},
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{"G5FPW1_PGD0_PG_STS", BIT(27)},
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{"ACE_PGD6_PG_STS", BIT(29)},
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{"GBETSN1_PGD0_PG_STS", BIT(31)},
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{}
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};
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const struct pmc_bit_map *mtl_ioem_lpm_maps[] = {
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mtl_ioep_clocksource_status_map,
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mtl_ioep_power_gating_status_0_map,
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mtl_ioem_power_gating_status_1_map,
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mtl_ioep_power_gating_status_2_map,
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mtl_ioep_d3_status_0_map,
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mtl_ioep_d3_status_1_map,
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mtl_ioep_d3_status_2_map,
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mtl_ioep_d3_status_3_map,
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mtl_ioep_vnn_req_status_0_map,
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mtl_ioep_vnn_req_status_1_map,
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mtl_ioep_vnn_req_status_2_map,
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mtl_ioep_vnn_req_status_3_map,
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mtl_ioep_vnn_misc_status_map,
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mtl_socm_signal_status_map,
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NULL
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};
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const struct pmc_reg_map mtl_ioem_reg_map = {
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.regmap_length = MTL_IOE_PMC_MMIO_REG_LEN,
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.pfear_sts = ext_mtl_ioem_pfear_map,
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.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
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.ppfear_buckets = MTL_IOE_PPFEAR_NUM_ENTRIES,
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.lpm_status_offset = MTL_LPM_STATUS_OFFSET,
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.lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
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.lpm_sts = mtl_ioem_lpm_maps,
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.ltr_show_sts = mtl_ioep_ltr_show_map,
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.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
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.ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,
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};
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#define PMC_DEVID_SOCM 0x7e7f
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#define PMC_DEVID_IOEP 0x7ecf
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#define PMC_DEVID_IOEM 0x7ebf
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static struct pmc_info mtl_pmc_info_list[] = {
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{
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.devid = PMC_DEVID_SOCM,
@@ -795,6 +936,10 @@ static struct pmc_info mtl_pmc_info_list[] = {
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.devid = PMC_DEVID_IOEP,
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.map = &mtl_ioep_reg_map,
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},
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{
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.devid = PMC_DEVID_IOEM,
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.map = &mtl_ioem_reg_map
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},
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{}
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};
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