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Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and 'clk-cleanup' into clk-next
 - Remove OXNAS clk driver * clk-bindings: dt-bindings: clock: versal: Convert the xlnx,zynqmp-clk.txt to yaml dt-bindings: clock: xlnx,versal-clk: drop select:false dt-bindings: clock: versal: Add versal-net compatible string dt-bindings: clock: ast2600: Add I3C and MAC reset definitions dt-bindings: arm: hisilicon,cpuctrl: Merge "hisilicon,hix5hd2-clock" into parent binding * clk-starfive: reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets support clk: starfive: Simplify .determine_rate() clk: starfive: Add StarFive JH7110 Video-Output clock driver clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver clk: starfive: Add StarFive JH7110 System-Top-Group clock driver clk: starfive: jh7110-sys: Add PLL clocks source from DTS clk: starfive: Add StarFive JH7110 PLL clock driver dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs dt-bindings: soc: starfive: Add StarFive syscon module dt-bindings: clock: Add StarFive JH7110 PLL clock generator * clk-rm: dt-bindings: clk: oxnas: remove obsolete bindings clk: oxnas: remove obsolete clock driver * clk-renesas: clk: renesas: rcar-gen3: Add ADG clocks clk: renesas: r8a77965: Add 3DGE and ZG support clk: renesas: r8a7796: Add 3DGE and ZG support clk: renesas: r8a7795: Add 3DGE and ZG support clk: renesas: emev2: Remove obsolete clkdev registration clk: renesas: r9a07g043: Add MTU3a clock and reset entry clk: renesas: rzg2l: Simplify .determine_rate() clk: renesas: r9a09g011: Add CSI related clocks clk: renesas: r8a774b1: Add 3DGE and ZG support clk: renesas: r8a774e1: Add 3DGE and ZG support clk: renesas: r8a774a1: Add 3DGE and ZG support clk: renesas: rcar-gen3: Add support for ZG clock * clk-cleanup: clk: mvebu: Convert to devm_platform_ioremap_resource() clk: nuvoton: Convert to devm_platform_ioremap_resource() clk: socfpga: agilex: Convert to devm_platform_ioremap_resource() clk: ti: Use devm_platform_get_and_ioremap_resource() clk: mediatek: Convert to devm_platform_ioremap_resource() clk: hsdk-pll: Convert to devm_platform_ioremap_resource() clk: gemini: Convert to devm_platform_ioremap_resource() clk: fsl-sai: Convert to devm_platform_ioremap_resource() clk: bm1880: Convert to devm_platform_ioremap_resource() clk: axm5516: Convert to devm_platform_ioremap_resource() clk: actions: Convert to devm_platform_ioremap_resource() clk: cdce925: Remove redundant of_match_ptr() drivers: clk: keystone: Fix parameter judgment in _of_pll_clk_init() clk: Explicitly include correct DT includes
5 parents 03d4a10 + 0e2b2a7 + 096110a + 772b455 + 0a26c3f commit d10ebc7

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‎Documentation/devicetree/bindings/clock/oxnas,stdclk.txt

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This file was deleted.

‎Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator
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maintainers:
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- Xingyu Wu <xingyu.wu@starfivetech.com>
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properties:
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compatible:
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const: starfive,jh7110-ispcrg
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reg:
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maxItems: 1
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clocks:
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items:
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- description: ISP Top core
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- description: ISP Top Axi
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- description: NOC ISP Bus
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- description: external DVP
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clock-names:
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items:
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- const: isp_top_core
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- const: isp_top_axi
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- const: noc_bus_isp_axi
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- const: dvp_clk
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resets:
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items:
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- description: ISP Top core
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- description: ISP Top Axi
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- description: NOC ISP Bus
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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'#reset-cells':
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const: 1
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description:
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See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
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power-domains:
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maxItems: 1
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description:
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ISP domain power
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- '#clock-cells'
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- '#reset-cells'
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- power-domains
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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#include <dt-bindings/power/starfive,jh7110-pmu.h>
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#include <dt-bindings/reset/starfive,jh7110-crg.h>
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ispcrg: clock-controller@19810000 {
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compatible = "starfive,jh7110-ispcrg";
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reg = <0x19810000 0x10000>;
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clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
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<&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
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<&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
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<&dvp_clk>;
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clock-names = "isp_top_core", "isp_top_axi",
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"noc_bus_isp_axi", "dvp_clk";
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resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
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<&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
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<&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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power-domains = <&pwrc JH7110_PD_ISP>;
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};

‎Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 PLL Clock Generator
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description:
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These PLLs are high speed, low jitter frequency synthesizers in the JH7110.
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Each PLL works in integer mode or fraction mode, with configuration
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registers in the sys syscon. So the PLLs node should be a child of
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SYS-SYSCON node.
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The formula for calculating frequency is
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Fvco = Fref * (NI + NF) / M / Q1
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maintainers:
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- Xingyu Wu <xingyu.wu@starfivetech.com>
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properties:
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compatible:
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const: starfive,jh7110-pll
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clocks:
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maxItems: 1
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description: Main Oscillator (24 MHz)
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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required:
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- compatible
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- clocks
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller {
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compatible = "starfive,jh7110-pll";
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clocks = <&osc>;
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#clock-cells = <1>;
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};

‎Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 System-Top-Group Clock and Reset Generator
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maintainers:
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- Xingyu Wu <xingyu.wu@starfivetech.com>
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properties:
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compatible:
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const: starfive,jh7110-stgcrg
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Main Oscillator (24 MHz)
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- description: HIFI4 core
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- description: STG AXI/AHB
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- description: USB (125 MHz)
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- description: CPU Bus
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- description: HIFI4 Axi
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- description: NOC STG Bus
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- description: APB Bus
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clock-names:
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items:
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- const: osc
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- const: hifi4_core
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- const: stg_axiahb
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- const: usb_125m
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- const: cpu_bus
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- const: hifi4_axi
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- const: nocstg_bus
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- const: apb_bus
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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'#reset-cells':
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const: 1
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description:
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See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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stgcrg: clock-controller@10230000 {
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compatible = "starfive,jh7110-stgcrg";
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reg = <0x10230000 0x10000>;
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clocks = <&osc>,
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<&syscrg JH7110_SYSCLK_HIFI4_CORE>,
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<&syscrg JH7110_SYSCLK_STG_AXIAHB>,
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<&syscrg JH7110_SYSCLK_USB_125M>,
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<&syscrg JH7110_SYSCLK_CPU_BUS>,
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<&syscrg JH7110_SYSCLK_HIFI4_AXI>,
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<&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
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<&syscrg JH7110_SYSCLK_APB_BUS>;
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clock-names = "osc", "hifi4_core",
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"stg_axiahb", "usb_125m",
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"cpu_bus", "hifi4_axi",
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"nocstg_bus", "apb_bus";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};

‎Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml

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@@ -27,6 +27,9 @@ properties:
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- description: External I2S RX left/right channel clock
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- description: External TDM clock
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- description: External audio master clock
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- description: PLL0
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- description: PLL1
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- description: PLL2
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- items:
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- description: Main Oscillator (24 MHz)
@@ -38,6 +41,9 @@ properties:
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- description: External I2S RX left/right channel clock
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- description: External TDM clock
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- description: External audio master clock
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- description: PLL0
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- description: PLL1
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- description: PLL2
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4248
clock-names:
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oneOf:
@@ -52,6 +58,9 @@ properties:
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- const: i2srx_lrck_ext
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- const: tdm_ext
5460
- const: mclk_ext
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- const: pll0_out
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- const: pll1_out
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- const: pll2_out
5564

5665
- items:
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- const: osc
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- const: i2srx_lrck_ext
6473
- const: tdm_ext
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- const: mclk_ext
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- const: pll0_out
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- const: pll1_out
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- const: pll2_out
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6779
'#clock-cells':
6880
const: 1
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<&gmac1_rgmii_rxin>,
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<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
95107
<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
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<&tdm_ext>, <&mclk_ext>;
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<&tdm_ext>, <&mclk_ext>,
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<&pllclk 0>, <&pllclk 1>, <&pllclk 2>;
97110
clock-names = "osc", "gmac1_rmii_refin",
98111
"gmac1_rgmii_rxin",
99112
"i2stx_bclk_ext", "i2stx_lrck_ext",
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"i2srx_bclk_ext", "i2srx_lrck_ext",
101-
"tdm_ext", "mclk_ext";
114+
"tdm_ext", "mclk_ext",
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"pll0_out", "pll1_out", "pll2_out";
102116
#clock-cells = <1>;
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#reset-cells = <1>;
104118
};

‎Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 Video-Output Clock and Reset Generator
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maintainers:
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- Xingyu Wu <xingyu.wu@starfivetech.com>
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12+
properties:
13+
compatible:
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const: starfive,jh7110-voutcrg
15+
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Vout Top core
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- description: Vout Top Ahb
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- description: Vout Top Axi
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- description: Vout Top HDMI MCLK
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- description: I2STX0 BCLK
26+
- description: external HDMI pixel
27+
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clock-names:
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items:
30+
- const: vout_src
31+
- const: vout_top_ahb
32+
- const: vout_top_axi
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- const: vout_top_hdmitx0_mclk
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- const: i2stx0_bclk
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- const: hdmitx0_pixelclk
36+
37+
resets:
38+
maxItems: 1
39+
description: Vout Top core
40+
41+
'#clock-cells':
42+
const: 1
43+
description:
44+
See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
45+
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'#reset-cells':
47+
const: 1
48+
description:
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See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
50+
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power-domains:
52+
maxItems: 1
53+
description:
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Vout domain power
55+
56+
required:
57+
- compatible
58+
- reg
59+
- clocks
60+
- clock-names
61+
- resets
62+
- '#clock-cells'
63+
- '#reset-cells'
64+
- power-domains
65+
66+
additionalProperties: false
67+
68+
examples:
69+
- |
70+
#include <dt-bindings/clock/starfive,jh7110-crg.h>
71+
#include <dt-bindings/power/starfive,jh7110-pmu.h>
72+
#include <dt-bindings/reset/starfive,jh7110-crg.h>
73+
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voutcrg: clock-controller@295C0000 {
75+
compatible = "starfive,jh7110-voutcrg";
76+
reg = <0x295C0000 0x10000>;
77+
clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
78+
<&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
79+
<&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
80+
<&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
81+
<&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
82+
<&hdmitx0_pixelclk>;
83+
clock-names = "vout_src", "vout_top_ahb",
84+
"vout_top_axi", "vout_top_hdmitx0_mclk",
85+
"i2stx0_bclk", "hdmitx0_pixelclk";
86+
resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
87+
#clock-cells = <1>;
88+
#reset-cells = <1>;
89+
power-domains = <&pwrc JH7110_PD_VOUT>;
90+
};

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