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Merge tag 'perf-core-2022-05-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull perf events updates from Ingo Molnar: "Platform PMU changes: - x86/intel: - Add new Intel Alder Lake and Raptor Lake support - x86/amd: - AMD Zen4 IBS extensions support - Add AMD PerfMonV2 support - Add AMD Fam19h Branch Sampling support Generic changes: - signal: Deliver SIGTRAP on perf event asynchronously if blocked Perf instrumentation can be driven via SIGTRAP, but this causes a problem when SIGTRAP is blocked by a task & terminate the task. Allow user-space to request these signals asynchronously (after they get unblocked) & also give the information to the signal handler when this happens: "To give user space the ability to clearly distinguish synchronous from asynchronous signals, introduce siginfo_t::si_perf_flags and TRAP_PERF_FLAG_ASYNC (opted for flags in case more binary information is required in future). The resolution to the problem is then to (a) no longer force the signal (avoiding the terminations), but (b) tell user space via si_perf_flags if the signal was synchronous or not, so that such signals can be handled differently (e.g. let user space decide to ignore or consider the data imprecise). " - Unify/standardize the /sys/devices/cpu/events/* output format. - Misc fixes & cleanups" * tag 'perf-core-2022-05-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (32 commits) perf/x86/amd/core: Fix reloading events for SVM perf/x86/amd: Run AMD BRS code only on supported hw perf/x86/amd: Fix AMD BRS period adjustment perf/x86/amd: Remove unused variable 'hwc' perf/ibs: Fix comment perf/amd/ibs: Advertise zen4_ibs_extensions as pmu capability attribute perf/amd/ibs: Add support for L3 miss filtering perf/amd/ibs: Use ->is_visible callback for dynamic attributes perf/amd/ibs: Cascade pmu init functions' return value perf/x86/uncore: Add new Alder Lake and Raptor Lake support perf/x86/uncore: Clean up uncore_pci_ids[] perf/x86/cstate: Add new Alder Lake and Raptor Lake support perf/x86/msr: Add new Alder Lake and Raptor Lake support perf/x86: Add new Alder Lake and Raptor Lake support perf/amd/ibs: Use interrupt regs ip for stack unwinding perf/x86/amd/core: Add PerfMonV2 overflow handling perf/x86/amd/core: Add PerfMonV2 counter control perf/x86/amd/core: Detect available counters perf/x86/amd/core: Detect PerfMonV2 support x86/msr: Add PerfCntrGlobal* registers ...
2 parents 22922de + bae19fd commit cfeb252

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‎arch/arm/kernel/signal.c

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@@ -708,6 +708,7 @@ static_assert(offsetof(siginfo_t, si_upper) == 0x18);
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static_assert(offsetof(siginfo_t, si_pkey) == 0x14);
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static_assert(offsetof(siginfo_t, si_perf_data) == 0x10);
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static_assert(offsetof(siginfo_t, si_perf_type) == 0x14);
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static_assert(offsetof(siginfo_t, si_perf_flags) == 0x18);
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static_assert(offsetof(siginfo_t, si_band) == 0x0c);
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static_assert(offsetof(siginfo_t, si_fd) == 0x10);
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static_assert(offsetof(siginfo_t, si_call_addr) == 0x0c);

‎arch/arm64/kernel/signal.c

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@@ -1179,6 +1179,7 @@ static_assert(offsetof(siginfo_t, si_upper) == 0x28);
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static_assert(offsetof(siginfo_t, si_pkey) == 0x20);
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static_assert(offsetof(siginfo_t, si_perf_data) == 0x18);
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static_assert(offsetof(siginfo_t, si_perf_type) == 0x20);
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static_assert(offsetof(siginfo_t, si_perf_flags) == 0x24);
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static_assert(offsetof(siginfo_t, si_band) == 0x10);
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static_assert(offsetof(siginfo_t, si_fd) == 0x18);
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static_assert(offsetof(siginfo_t, si_call_addr) == 0x10);

‎arch/arm64/kernel/signal32.c

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@@ -487,6 +487,7 @@ static_assert(offsetof(compat_siginfo_t, si_upper) == 0x18);
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static_assert(offsetof(compat_siginfo_t, si_pkey) == 0x14);
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static_assert(offsetof(compat_siginfo_t, si_perf_data) == 0x10);
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static_assert(offsetof(compat_siginfo_t, si_perf_type) == 0x14);
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static_assert(offsetof(compat_siginfo_t, si_perf_flags) == 0x18);
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static_assert(offsetof(compat_siginfo_t, si_band) == 0x0c);
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static_assert(offsetof(compat_siginfo_t, si_fd) == 0x10);
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static_assert(offsetof(compat_siginfo_t, si_call_addr) == 0x0c);

‎arch/m68k/kernel/signal.c

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@@ -625,6 +625,7 @@ static inline void siginfo_build_tests(void)
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/* _sigfault._perf */
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BUILD_BUG_ON(offsetof(siginfo_t, si_perf_data) != 0x10);
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BUILD_BUG_ON(offsetof(siginfo_t, si_perf_type) != 0x14);
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BUILD_BUG_ON(offsetof(siginfo_t, si_perf_flags) != 0x18);
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/* _sigpoll */
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BUILD_BUG_ON(offsetof(siginfo_t, si_band) != 0x0c);

‎arch/sparc/kernel/signal32.c

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@@ -779,5 +779,6 @@ static_assert(offsetof(compat_siginfo_t, si_upper) == 0x18);
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static_assert(offsetof(compat_siginfo_t, si_pkey) == 0x14);
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static_assert(offsetof(compat_siginfo_t, si_perf_data) == 0x10);
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static_assert(offsetof(compat_siginfo_t, si_perf_type) == 0x14);
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static_assert(offsetof(compat_siginfo_t, si_perf_flags) == 0x18);
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static_assert(offsetof(compat_siginfo_t, si_band) == 0x0c);
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static_assert(offsetof(compat_siginfo_t, si_fd) == 0x10);

‎arch/sparc/kernel/signal_64.c

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@@ -590,5 +590,6 @@ static_assert(offsetof(siginfo_t, si_upper) == 0x28);
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static_assert(offsetof(siginfo_t, si_pkey) == 0x20);
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static_assert(offsetof(siginfo_t, si_perf_data) == 0x18);
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static_assert(offsetof(siginfo_t, si_perf_type) == 0x20);
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static_assert(offsetof(siginfo_t, si_perf_flags) == 0x24);
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static_assert(offsetof(siginfo_t, si_band) == 0x10);
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static_assert(offsetof(siginfo_t, si_fd) == 0x14);

‎arch/x86/events/Kconfig

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@@ -44,4 +44,12 @@ config PERF_EVENTS_AMD_UNCORE
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To compile this driver as a module, choose M here: the
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module will be called 'amd-uncore'.
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config PERF_EVENTS_AMD_BRS
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depends on PERF_EVENTS && CPU_SUP_AMD
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bool "AMD Zen3 Branch Sampling support"
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help
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Enable AMD Zen3 branch sampling support (BRS) which samples up to
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16 consecutive taken branches in registers.
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endmenu

‎arch/x86/events/amd/Makefile

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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_CPU_SUP_AMD) += core.o
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obj-$(CONFIG_PERF_EVENTS_AMD_BRS) += brs.o
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obj-$(CONFIG_PERF_EVENTS_AMD_POWER) += power.o
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obj-$(CONFIG_X86_LOCAL_APIC) += ibs.o
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obj-$(CONFIG_PERF_EVENTS_AMD_UNCORE) += amd-uncore.o

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