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Kan LiangPeter Zijlstra
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perf/x86/intel: Fix pebs event constraints for ADL
According to the latest event list, the LOAD_LATENCY PEBS event only works on the GP counter 0 and 1 for ADL and RPL. Update the pebs event constraints table. Fixes: f83d2f9 ("perf/x86/intel: Add Alder Lake Hybrid support") Reported-by: Ammy Yi <ammy.yi@intel.com> Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20220818184429.2355857-1-kan.liang@linux.intel.com
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arch/x86/events/intel/ds.c

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@@ -830,7 +830,7 @@ struct event_constraint intel_glm_pebs_event_constraints[] = {
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struct event_constraint intel_grt_pebs_event_constraints[] = {
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/* Allow all events as PEBS with no flags */
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INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0xf),
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INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0x3),
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INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xf),
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EVENT_CONSTRAINT_END
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};

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