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Merge patch series "riscv: hwprobe: add Zicond, Zacas and Ztso support"
Clément Léger <cleger@rivosinc.com> says: This series add support for a few more extensions that are present in the RVA22U64/RVA23U64 (either mandatory or optional) and that are useful for userspace: - Zicond - Zacas - Ztso Series currently based on riscv/for-next. * b4-shazam-lts: riscv: hwprobe: export Zicond extension riscv: hwprobe: export Zacas ISA extension riscv: add ISA extension parsing for Zacas dt-bindings: riscv: add Zacas ISA extension description riscv: hwprobe: export Ztso ISA extension riscv: add ISA extension parsing for Ztso Link: https://lore.kernel.org/r/20231220155723.684081-1-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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Documentation/arch/riscv/hwprobe.rst

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@@ -175,6 +175,19 @@ The following keys are defined:
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defined in the RISC-V ISA manual starting from commit 056b6ff467c7
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("Zfa is ratified").
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* :c:macro:`RISCV_HWPROBE_EXT_ZTSO`: The Ztso extension is supported as
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defined in the RISC-V ISA manual starting from commit 5618fb5a216b
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("Ztso is now ratified.")
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* :c:macro:`RISCV_HWPROBE_EXT_ZACAS`: The Zacas extension is supported as
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defined in the Atomic Compare-and-Swap (CAS) instructions manual starting
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from commit 5059e0ca641c ("update to ratified").
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* :c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported as
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defined in the RISC-V Integer Conditional (Zicond) operations extension
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manual starting from commit 95cf1f9 ("Add changes requested by Ved
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during signoff")
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* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
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information about the selected set of processors.
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Documentation/devicetree/bindings/riscv/extensions.yaml

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@@ -171,6 +171,12 @@ properties:
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memory types as ratified in the 20191213 version of the privileged
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ISA specification.
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- const: zacas
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description: |
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The Zacas extension for Atomic Compare-and-Swap (CAS) instructions
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is supported as ratified at commit 5059e0ca641c ("update to
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ratified") of the riscv-zacas.
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- const: zba
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description: |
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The standard Zba bit-manipulation extension for address generation

arch/riscv/include/asm/hwcap.h

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@@ -78,6 +78,8 @@
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#define RISCV_ISA_EXT_ZVFH 69
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#define RISCV_ISA_EXT_ZVFHMIN 70
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#define RISCV_ISA_EXT_ZFA 71
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#define RISCV_ISA_EXT_ZTSO 72
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#define RISCV_ISA_EXT_ZACAS 73
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#define RISCV_ISA_EXT_MAX 128
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#define RISCV_ISA_EXT_INVALID U32_MAX

arch/riscv/include/uapi/asm/hwprobe.h

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@@ -56,6 +56,9 @@ struct riscv_hwprobe {
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#define RISCV_HWPROBE_EXT_ZVFH (1 << 30)
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#define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 31)
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#define RISCV_HWPROBE_EXT_ZFA (1ULL << 32)
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#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33)
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#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
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#define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
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#define RISCV_HWPROBE_KEY_CPUPERF_0 5
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#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
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#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)

arch/riscv/kernel/cpufeature.c

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@@ -255,6 +255,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
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__RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL),
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__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
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__RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
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__RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),
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__RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),
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__RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),
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__RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
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__RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT),
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__RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED),
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__RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH),
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__RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),
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__RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),
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__RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
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__RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),

arch/riscv/kernel/sys_hwprobe.c

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@@ -108,6 +108,9 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
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EXT_KEY(ZKSH);
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EXT_KEY(ZKT);
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EXT_KEY(ZIHINTNTL);
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EXT_KEY(ZTSO);
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EXT_KEY(ZACAS);
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EXT_KEY(ZICOND);
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if (has_vector()) {
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EXT_KEY(ZVBB);

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