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abrodkinVineet Gupta
abrodkin
authored and
Vineet Gupta
committed
arc: perf: Move static structs to where they're really used
It is all well described by Stephen Rothwell who initially spotted that: ----------------------------->8---------------------------- After merging the origin tree, today's linux-next build (arc haps_hs_smp_defconfig+kselftest) produced these warnings: arch/arc/include/asm/perf_event.h:126:27: warning: 'arc_pmu_cache_map' defined but not used [-Wunused-const-variable=] arch/arc/include/asm/perf_event.h:91:27: warning: 'arc_pmu_ev_hw_map' defined but not used [-Wunused-const-variable=] Introduced by commit 0dd450f ("ARC: Add perf support for ARC700 cores") The 2 static arrays should be moved into arch/arc/kernel/perf_event.c (the only place that uses them). We get the warning because perf_event.h is also included by arch/arc/kernel/unaligned.c. ----------------------------->8---------------------------- Could be easily reproduced by running make with "W=1" on any up-to-date sources, when extra warnings get enabled (in particular "-Wunused-const-variable"), otherwise disabled by default in the top-level Makefile as "These warnings generated too much noise in a regular build". Cc: Mischa Jonker <mjonker@synopsys.com> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@kernel.org>
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‎arch/arc/include/asm/perf_event.h

Lines changed: 0 additions & 162 deletions
Original file line numberDiff line numberDiff line change
@@ -63,166 +63,4 @@ struct arc_reg_cc_build {
6363

6464
#define PERF_COUNT_ARC_HW_MAX (PERF_COUNT_HW_MAX + 8)
6565

66-
/*
67-
* Some ARC pct quirks:
68-
*
69-
* PERF_COUNT_HW_STALLED_CYCLES_BACKEND
70-
* PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
71-
* The ARC 700 can either measure stalls per pipeline stage, or all stalls
72-
* combined; for now we assign all stalls to STALLED_CYCLES_BACKEND
73-
* and all pipeline flushes (e.g. caused by mispredicts, etc.) to
74-
* STALLED_CYCLES_FRONTEND.
75-
*
76-
* We could start multiple performance counters and combine everything
77-
* afterwards, but that makes it complicated.
78-
*
79-
* Note that I$ cache misses aren't counted by either of the two!
80-
*/
81-
82-
/*
83-
* ARC PCT has hardware conditions with fixed "names" but variable "indexes"
84-
* (based on a specific RTL build)
85-
* Below is the static map between perf generic/arc specific event_id and
86-
* h/w condition names.
87-
* At the time of probe, we loop thru each index and find it's name to
88-
* complete the mapping of perf event_id to h/w index as latter is needed
89-
* to program the counter really
90-
*/
91-
static const char * const arc_pmu_ev_hw_map[] = {
92-
/* count cycles */
93-
[PERF_COUNT_HW_CPU_CYCLES] = "crun",
94-
[PERF_COUNT_HW_REF_CPU_CYCLES] = "crun",
95-
[PERF_COUNT_HW_BUS_CYCLES] = "crun",
96-
97-
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = "bflush",
98-
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = "bstall",
99-
100-
/* counts condition */
101-
[PERF_COUNT_HW_INSTRUCTIONS] = "iall",
102-
/* All jump instructions that are taken */
103-
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmptak",
104-
#ifdef CONFIG_ISA_ARCV2
105-
[PERF_COUNT_HW_BRANCH_MISSES] = "bpmp",
106-
#else
107-
[PERF_COUNT_ARC_BPOK] = "bpok", /* NP-NT, PT-T, PNT-NT */
108-
[PERF_COUNT_HW_BRANCH_MISSES] = "bpfail", /* NP-T, PT-NT, PNT-T */
109-
#endif
110-
[PERF_COUNT_ARC_LDC] = "imemrdc", /* Instr: mem read cached */
111-
[PERF_COUNT_ARC_STC] = "imemwrc", /* Instr: mem write cached */
112-
113-
[PERF_COUNT_ARC_DCLM] = "dclm", /* D-cache Load Miss */
114-
[PERF_COUNT_ARC_DCSM] = "dcsm", /* D-cache Store Miss */
115-
[PERF_COUNT_ARC_ICM] = "icm", /* I-cache Miss */
116-
[PERF_COUNT_ARC_EDTLB] = "edtlb", /* D-TLB Miss */
117-
[PERF_COUNT_ARC_EITLB] = "eitlb", /* I-TLB Miss */
118-
119-
[PERF_COUNT_HW_CACHE_REFERENCES] = "imemrdc", /* Instr: mem read cached */
120-
[PERF_COUNT_HW_CACHE_MISSES] = "dclm", /* D-cache Load Miss */
121-
};
122-
123-
#define C(_x) PERF_COUNT_HW_CACHE_##_x
124-
#define CACHE_OP_UNSUPPORTED 0xffff
125-
126-
static const unsigned int arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
127-
[C(L1D)] = {
128-
[C(OP_READ)] = {
129-
[C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC,
130-
[C(RESULT_MISS)] = PERF_COUNT_ARC_DCLM,
131-
},
132-
[C(OP_WRITE)] = {
133-
[C(RESULT_ACCESS)] = PERF_COUNT_ARC_STC,
134-
[C(RESULT_MISS)] = PERF_COUNT_ARC_DCSM,
135-
},
136-
[C(OP_PREFETCH)] = {
137-
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
138-
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
139-
},
140-
},
141-
[C(L1I)] = {
142-
[C(OP_READ)] = {
143-
[C(RESULT_ACCESS)] = PERF_COUNT_HW_INSTRUCTIONS,
144-
[C(RESULT_MISS)] = PERF_COUNT_ARC_ICM,
145-
},
146-
[C(OP_WRITE)] = {
147-
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
148-
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
149-
},
150-
[C(OP_PREFETCH)] = {
151-
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
152-
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
153-
},
154-
},
155-
[C(LL)] = {
156-
[C(OP_READ)] = {
157-
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
158-
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
159-
},
160-
[C(OP_WRITE)] = {
161-
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
162-
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
163-
},
164-
[C(OP_PREFETCH)] = {
165-
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
166-
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
167-
},
168-
},
169-
[C(DTLB)] = {
170-
[C(OP_READ)] = {
171-
[C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC,
172-
[C(RESULT_MISS)] = PERF_COUNT_ARC_EDTLB,
173-
},
174-
/* DTLB LD/ST Miss not segregated by h/w*/
175-
[C(OP_WRITE)] = {
176-
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
177-
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
178-
},
179-
[C(OP_PREFETCH)] = {
180-
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
181-
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
182-
},
183-
},
184-
[C(ITLB)] = {
185-
[C(OP_READ)] = {
186-
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
187-
[C(RESULT_MISS)] = PERF_COUNT_ARC_EITLB,
188-
},
189-
[C(OP_WRITE)] = {
190-
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
191-
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
192-
},
193-
[C(OP_PREFETCH)] = {
194-
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
195-
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
196-
},
197-
},
198-
[C(BPU)] = {
199-
[C(OP_READ)] = {
200-
[C(RESULT_ACCESS)] = PERF_COUNT_HW_BRANCH_INSTRUCTIONS,
201-
[C(RESULT_MISS)] = PERF_COUNT_HW_BRANCH_MISSES,
202-
},
203-
[C(OP_WRITE)] = {
204-
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
205-
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
206-
},
207-
[C(OP_PREFETCH)] = {
208-
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
209-
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
210-
},
211-
},
212-
[C(NODE)] = {
213-
[C(OP_READ)] = {
214-
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
215-
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
216-
},
217-
[C(OP_WRITE)] = {
218-
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
219-
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
220-
},
221-
[C(OP_PREFETCH)] = {
222-
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
223-
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
224-
},
225-
},
226-
};
227-
22866
#endif /* __ASM_PERF_EVENT_H */

‎arch/arc/kernel/perf_event.c

Lines changed: 162 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,168 @@
1717
/* HW holds 8 symbols + one for null terminator */
1818
#define ARCPMU_EVENT_NAME_LEN 9
1919

20+
/*
21+
* Some ARC pct quirks:
22+
*
23+
* PERF_COUNT_HW_STALLED_CYCLES_BACKEND
24+
* PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
25+
* The ARC 700 can either measure stalls per pipeline stage, or all stalls
26+
* combined; for now we assign all stalls to STALLED_CYCLES_BACKEND
27+
* and all pipeline flushes (e.g. caused by mispredicts, etc.) to
28+
* STALLED_CYCLES_FRONTEND.
29+
*
30+
* We could start multiple performance counters and combine everything
31+
* afterwards, but that makes it complicated.
32+
*
33+
* Note that I$ cache misses aren't counted by either of the two!
34+
*/
35+
36+
/*
37+
* ARC PCT has hardware conditions with fixed "names" but variable "indexes"
38+
* (based on a specific RTL build)
39+
* Below is the static map between perf generic/arc specific event_id and
40+
* h/w condition names.
41+
* At the time of probe, we loop thru each index and find it's name to
42+
* complete the mapping of perf event_id to h/w index as latter is needed
43+
* to program the counter really
44+
*/
45+
static const char * const arc_pmu_ev_hw_map[] = {
46+
/* count cycles */
47+
[PERF_COUNT_HW_CPU_CYCLES] = "crun",
48+
[PERF_COUNT_HW_REF_CPU_CYCLES] = "crun",
49+
[PERF_COUNT_HW_BUS_CYCLES] = "crun",
50+
51+
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = "bflush",
52+
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = "bstall",
53+
54+
/* counts condition */
55+
[PERF_COUNT_HW_INSTRUCTIONS] = "iall",
56+
/* All jump instructions that are taken */
57+
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmptak",
58+
#ifdef CONFIG_ISA_ARCV2
59+
[PERF_COUNT_HW_BRANCH_MISSES] = "bpmp",
60+
#else
61+
[PERF_COUNT_ARC_BPOK] = "bpok", /* NP-NT, PT-T, PNT-NT */
62+
[PERF_COUNT_HW_BRANCH_MISSES] = "bpfail", /* NP-T, PT-NT, PNT-T */
63+
#endif
64+
[PERF_COUNT_ARC_LDC] = "imemrdc", /* Instr: mem read cached */
65+
[PERF_COUNT_ARC_STC] = "imemwrc", /* Instr: mem write cached */
66+
67+
[PERF_COUNT_ARC_DCLM] = "dclm", /* D-cache Load Miss */
68+
[PERF_COUNT_ARC_DCSM] = "dcsm", /* D-cache Store Miss */
69+
[PERF_COUNT_ARC_ICM] = "icm", /* I-cache Miss */
70+
[PERF_COUNT_ARC_EDTLB] = "edtlb", /* D-TLB Miss */
71+
[PERF_COUNT_ARC_EITLB] = "eitlb", /* I-TLB Miss */
72+
73+
[PERF_COUNT_HW_CACHE_REFERENCES] = "imemrdc", /* Instr: mem read cached */
74+
[PERF_COUNT_HW_CACHE_MISSES] = "dclm", /* D-cache Load Miss */
75+
};
76+
77+
#define C(_x) PERF_COUNT_HW_CACHE_##_x
78+
#define CACHE_OP_UNSUPPORTED 0xffff
79+
80+
static const unsigned int arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
81+
[C(L1D)] = {
82+
[C(OP_READ)] = {
83+
[C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC,
84+
[C(RESULT_MISS)] = PERF_COUNT_ARC_DCLM,
85+
},
86+
[C(OP_WRITE)] = {
87+
[C(RESULT_ACCESS)] = PERF_COUNT_ARC_STC,
88+
[C(RESULT_MISS)] = PERF_COUNT_ARC_DCSM,
89+
},
90+
[C(OP_PREFETCH)] = {
91+
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
92+
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
93+
},
94+
},
95+
[C(L1I)] = {
96+
[C(OP_READ)] = {
97+
[C(RESULT_ACCESS)] = PERF_COUNT_HW_INSTRUCTIONS,
98+
[C(RESULT_MISS)] = PERF_COUNT_ARC_ICM,
99+
},
100+
[C(OP_WRITE)] = {
101+
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
102+
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
103+
},
104+
[C(OP_PREFETCH)] = {
105+
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
106+
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
107+
},
108+
},
109+
[C(LL)] = {
110+
[C(OP_READ)] = {
111+
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
112+
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
113+
},
114+
[C(OP_WRITE)] = {
115+
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
116+
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
117+
},
118+
[C(OP_PREFETCH)] = {
119+
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
120+
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
121+
},
122+
},
123+
[C(DTLB)] = {
124+
[C(OP_READ)] = {
125+
[C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC,
126+
[C(RESULT_MISS)] = PERF_COUNT_ARC_EDTLB,
127+
},
128+
/* DTLB LD/ST Miss not segregated by h/w*/
129+
[C(OP_WRITE)] = {
130+
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
131+
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
132+
},
133+
[C(OP_PREFETCH)] = {
134+
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
135+
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
136+
},
137+
},
138+
[C(ITLB)] = {
139+
[C(OP_READ)] = {
140+
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
141+
[C(RESULT_MISS)] = PERF_COUNT_ARC_EITLB,
142+
},
143+
[C(OP_WRITE)] = {
144+
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
145+
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
146+
},
147+
[C(OP_PREFETCH)] = {
148+
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
149+
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
150+
},
151+
},
152+
[C(BPU)] = {
153+
[C(OP_READ)] = {
154+
[C(RESULT_ACCESS)] = PERF_COUNT_HW_BRANCH_INSTRUCTIONS,
155+
[C(RESULT_MISS)] = PERF_COUNT_HW_BRANCH_MISSES,
156+
},
157+
[C(OP_WRITE)] = {
158+
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
159+
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
160+
},
161+
[C(OP_PREFETCH)] = {
162+
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
163+
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
164+
},
165+
},
166+
[C(NODE)] = {
167+
[C(OP_READ)] = {
168+
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
169+
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
170+
},
171+
[C(OP_WRITE)] = {
172+
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
173+
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
174+
},
175+
[C(OP_PREFETCH)] = {
176+
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
177+
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
178+
},
179+
},
180+
};
181+
20182
enum arc_pmu_attr_groups {
21183
ARCPMU_ATTR_GR_EVENTS,
22184
ARCPMU_ATTR_GR_FORMATS,

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