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drm/etnaviv: unconditionally enable debug registers
A later change will use the FE debug registers to improve GPU progress monitoring. Instead of having to keep track of the usage state of the debug registers and lock access to the VIVS_HI_CLOCK_CONTROL register, statically enable debug register access during GPU init. The Vivante downstream driver seems to do the same thing since a while, so it should be okay to keep access enabled. (See gckHARDWARE_InitializeHardware in 6.4.11 downstream driver). Many debug registers contain bogus data if clock gating is enabled, so even if they are always accessible performance profiling still needs to manage some prerequisites. Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
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drivers/gpu/drm/etnaviv/etnaviv_gpu.c

Lines changed: 2 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -574,8 +574,8 @@ static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
574574
continue;
575575
}
576576

577-
/* disable debug registers, as they are not normally needed */
578-
control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
577+
/* enable debug register access */
578+
control &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
579579
gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
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581581
failed = false;
@@ -1329,11 +1329,6 @@ static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
13291329
val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
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gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val);
13311331

1332-
/* enable debug register */
1333-
val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1334-
val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1335-
gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1336-
13371332
sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
13381333

13391334
mutex_unlock(&gpu->lock);
@@ -1350,11 +1345,6 @@ static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
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13511346
sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
13521347

1353-
/* disable debug register */
1354-
val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1355-
val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1356-
gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1357-
13581348
/* enable clock gating */
13591349
val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
13601350
val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;

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