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airliedairlied
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Merge tag 'drm-intel-gt-next-2024-10-23' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next
Driver Changes: Fixes/improvements/new stuff: - Enable PXP GuC autoteardown flow [guc] (Juston Li) - Retry RING_HEAD reset until it get sticks [gt] (Nitin Gote) - Add basic PMU support for gen2 [pmu] (Ville Syrjälä) Miscellaneous: - Prevent a possible int overflow in wq offsets [guc] (Nikita Zhandarovich) - PMU code cleanups (Lucas De Marchi) - Fixed "CPU" -> "GPU" typo [gt] (Zhang He) - Gen2/3 interrupt handling cleanup (Ville Syrjälä) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Tvrtko Ursulin <tursulin@igalia.com> Link: https://patchwork.freedesktop.org/patch/msgid/Zxi-3wkIwI-Y1Qvj@linux
2 parents 0a4d0b2 + 6ef0e3e commit c9ff14d

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10 files changed

+80
-59
lines changed

10 files changed

+80
-59
lines changed

‎drivers/gpu/drm/i915/gt/gen2_engine_cs.c

Lines changed: 3 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -169,7 +169,7 @@ static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs,
169169
return cs;
170170
}
171171

172-
u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs)
172+
u32 *gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs)
173173
{
174174
return __gen2_emit_breadcrumb(rq, cs, 16, 8);
175175
}
@@ -248,7 +248,7 @@ int i830_emit_bb_start(struct i915_request *rq,
248248
return 0;
249249
}
250250

251-
int gen3_emit_bb_start(struct i915_request *rq,
251+
int gen2_emit_bb_start(struct i915_request *rq,
252252
u64 offset, u32 len,
253253
unsigned int dispatch_flags)
254254
{
@@ -291,30 +291,13 @@ int gen4_emit_bb_start(struct i915_request *rq,
291291
}
292292

293293
void gen2_irq_enable(struct intel_engine_cs *engine)
294-
{
295-
struct drm_i915_private *i915 = engine->i915;
296-
297-
i915->irq_mask &= ~engine->irq_enable_mask;
298-
intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask);
299-
ENGINE_POSTING_READ16(engine, RING_IMR);
300-
}
301-
302-
void gen2_irq_disable(struct intel_engine_cs *engine)
303-
{
304-
struct drm_i915_private *i915 = engine->i915;
305-
306-
i915->irq_mask |= engine->irq_enable_mask;
307-
intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask);
308-
}
309-
310-
void gen3_irq_enable(struct intel_engine_cs *engine)
311294
{
312295
engine->i915->irq_mask &= ~engine->irq_enable_mask;
313296
intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask);
314297
intel_uncore_posting_read_fw(engine->uncore, GEN2_IMR);
315298
}
316299

317-
void gen3_irq_disable(struct intel_engine_cs *engine)
300+
void gen2_irq_disable(struct intel_engine_cs *engine)
318301
{
319302
engine->i915->irq_mask |= engine->irq_enable_mask;
320303
intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask);

‎drivers/gpu/drm/i915/gt/gen2_engine_cs.h

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -15,13 +15,13 @@ int gen2_emit_flush(struct i915_request *rq, u32 mode);
1515
int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode);
1616
int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode);
1717

18-
u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs);
18+
u32 *gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs);
1919
u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs);
2020

2121
int i830_emit_bb_start(struct i915_request *rq,
2222
u64 offset, u32 len,
2323
unsigned int dispatch_flags);
24-
int gen3_emit_bb_start(struct i915_request *rq,
24+
int gen2_emit_bb_start(struct i915_request *rq,
2525
u64 offset, u32 len,
2626
unsigned int dispatch_flags);
2727
int gen4_emit_bb_start(struct i915_request *rq,
@@ -30,8 +30,6 @@ int gen4_emit_bb_start(struct i915_request *rq,
3030

3131
void gen2_irq_enable(struct intel_engine_cs *engine);
3232
void gen2_irq_disable(struct intel_engine_cs *engine);
33-
void gen3_irq_enable(struct intel_engine_cs *engine);
34-
void gen3_irq_disable(struct intel_engine_cs *engine);
3533
void gen5_irq_enable(struct intel_engine_cs *engine);
3634
void gen5_irq_disable(struct intel_engine_cs *engine);
3735

‎drivers/gpu/drm/i915/gt/intel_engine_regs.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
#define HEAD_WRAP_COUNT 0xFFE00000
1616
#define HEAD_WRAP_ONE 0x00200000
1717
#define HEAD_ADDR 0x001FFFFC
18+
#define HEAD_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */
1819
#define RING_START(base) _MMIO((base) + 0x38)
1920
#define RING_CTL(base) _MMIO((base) + 0x3c)
2021
#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
@@ -26,7 +27,6 @@
2627
#define RING_VALID_MASK 0x00000001
2728
#define RING_VALID 0x00000001
2829
#define RING_INVALID 0x00000000
29-
#define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */
3030
#define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */
3131
#define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */
3232
#define RING_SYNC_0(base) _MMIO((base) + 0x40)

‎drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -431,7 +431,7 @@ static int llc_show(struct seq_file *m, void *data)
431431
max_gpu_freq /= GEN9_FREQ_SCALER;
432432
}
433433

434-
seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
434+
seq_puts(m, "GPU freq (MHz)\tEffective GPU freq (MHz)\tEffective Ring freq (MHz)\n");
435435

436436
wakeref = intel_runtime_pm_get(gt->uncore->rpm);
437437
for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {

‎drivers/gpu/drm/i915/gt/intel_ring_submission.c

Lines changed: 29 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -192,6 +192,7 @@ static bool stop_ring(struct intel_engine_cs *engine)
192192
static int xcs_resume(struct intel_engine_cs *engine)
193193
{
194194
struct intel_ring *ring = engine->legacy.ring;
195+
ktime_t kt;
195196

196197
ENGINE_TRACE(engine, "ring:{HEAD:%04x, TAIL:%04x}\n",
197198
ring->head, ring->tail);
@@ -230,9 +231,27 @@ static int xcs_resume(struct intel_engine_cs *engine)
230231
set_pp_dir(engine);
231232

232233
/* First wake the ring up to an empty/idle ring */
233-
ENGINE_WRITE_FW(engine, RING_HEAD, ring->head);
234+
for ((kt) = ktime_get() + (2 * NSEC_PER_MSEC);
235+
ktime_before(ktime_get(), (kt)); cpu_relax()) {
236+
/*
237+
* In case of resets fails because engine resumes from
238+
* incorrect RING_HEAD and then GPU may be then fed
239+
* to invalid instrcutions, which may lead to unrecoverable
240+
* hang. So at first write doesn't succeed then try again.
241+
*/
242+
ENGINE_WRITE_FW(engine, RING_HEAD, ring->head);
243+
if (ENGINE_READ_FW(engine, RING_HEAD) == ring->head)
244+
break;
245+
}
246+
234247
ENGINE_WRITE_FW(engine, RING_TAIL, ring->head);
235-
ENGINE_POSTING_READ(engine, RING_TAIL);
248+
if (ENGINE_READ_FW(engine, RING_HEAD) != ENGINE_READ_FW(engine, RING_TAIL)) {
249+
ENGINE_TRACE(engine, "failed to reset empty ring: [%x, %x]: %x\n",
250+
ENGINE_READ_FW(engine, RING_HEAD),
251+
ENGINE_READ_FW(engine, RING_TAIL),
252+
ring->head);
253+
goto err;
254+
}
236255

237256
ENGINE_WRITE_FW(engine, RING_CTL,
238257
RING_CTL_SIZE(ring->size) | RING_VALID);
@@ -241,12 +260,16 @@ static int xcs_resume(struct intel_engine_cs *engine)
241260
if (__intel_wait_for_register_fw(engine->uncore,
242261
RING_CTL(engine->mmio_base),
243262
RING_VALID, RING_VALID,
244-
5000, 0, NULL))
263+
5000, 0, NULL)) {
264+
ENGINE_TRACE(engine, "failed to restart\n");
245265
goto err;
266+
}
246267

247-
if (GRAPHICS_VER(engine->i915) > 2)
268+
if (GRAPHICS_VER(engine->i915) > 2) {
248269
ENGINE_WRITE_FW(engine,
249270
RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
271+
ENGINE_POSTING_READ(engine, RING_MI_MODE);
272+
}
250273

251274
/* Now awake, let it get started */
252275
if (ring->tail != ring->head) {
@@ -1090,9 +1113,6 @@ static void setup_irq(struct intel_engine_cs *engine)
10901113
} else if (GRAPHICS_VER(i915) >= 5) {
10911114
engine->irq_enable = gen5_irq_enable;
10921115
engine->irq_disable = gen5_irq_disable;
1093-
} else if (GRAPHICS_VER(i915) >= 3) {
1094-
engine->irq_enable = gen3_irq_enable;
1095-
engine->irq_disable = gen3_irq_disable;
10961116
} else {
10971117
engine->irq_enable = gen2_irq_enable;
10981118
engine->irq_disable = gen2_irq_disable;
@@ -1146,7 +1166,7 @@ static void setup_common(struct intel_engine_cs *engine)
11461166
* equivalent to our next initial bread so we can elide
11471167
* engine->emit_init_breadcrumb().
11481168
*/
1149-
engine->emit_fini_breadcrumb = gen3_emit_breadcrumb;
1169+
engine->emit_fini_breadcrumb = gen2_emit_breadcrumb;
11501170
if (GRAPHICS_VER(i915) == 5)
11511171
engine->emit_fini_breadcrumb = gen5_emit_breadcrumb;
11521172

@@ -1159,7 +1179,7 @@ static void setup_common(struct intel_engine_cs *engine)
11591179
else if (IS_I830(i915) || IS_I845G(i915))
11601180
engine->emit_bb_start = i830_emit_bb_start;
11611181
else
1162-
engine->emit_bb_start = gen3_emit_bb_start;
1182+
engine->emit_bb_start = gen2_emit_bb_start;
11631183
}
11641184

11651185
static void setup_rcs(struct intel_engine_cs *engine)

‎drivers/gpu/drm/i915/gt/uc/intel_guc.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -239,8 +239,16 @@ static u32 guc_ctl_debug_flags(struct intel_guc *guc)
239239

240240
static u32 guc_ctl_feature_flags(struct intel_guc *guc)
241241
{
242+
struct intel_gt *gt = guc_to_gt(guc);
242243
u32 flags = 0;
243244

245+
/*
246+
* Enable PXP GuC autoteardown flow.
247+
* NB: MTL does things differently.
248+
*/
249+
if (HAS_PXP(gt->i915) && !IS_METEORLAKE(gt->i915))
250+
flags |= GUC_CTL_ENABLE_GUC_PXP_CTL;
251+
244252
if (!intel_guc_submission_is_used(guc))
245253
flags |= GUC_CTL_DISABLE_SCHEDULER;
246254

‎drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -105,6 +105,7 @@
105105
#define GUC_WA_ENABLE_TSC_CHECK_ON_RC6 BIT(22)
106106

107107
#define GUC_CTL_FEATURE 2
108+
#define GUC_CTL_ENABLE_GUC_PXP_CTL BIT(1)
108109
#define GUC_CTL_ENABLE_SLPC BIT(2)
109110
#define GUC_CTL_DISABLE_SCHEDULER BIT(14)
110111

‎drivers/gpu/drm/i915/i915_drv.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -691,6 +691,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
691691

692692
#define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps)
693693

694+
#define HAS_PXP(i915) \
695+
(IS_ENABLED(CONFIG_DRM_I915_PXP) && INTEL_INFO(i915)->has_pxp)
696+
694697
#define HAS_HECI_PXP(i915) \
695698
(INTEL_INFO(i915)->has_heci_pxp)
696699

‎drivers/gpu/drm/i915/i915_pmu.c

Lines changed: 31 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -356,7 +356,7 @@ static bool exclusive_mmio_access(const struct drm_i915_private *i915)
356356
return GRAPHICS_VER(i915) == 7;
357357
}
358358

359-
static void engine_sample(struct intel_engine_cs *engine, unsigned int period_ns)
359+
static void gen3_engine_sample(struct intel_engine_cs *engine, unsigned int period_ns)
360360
{
361361
struct intel_engine_pmu *pmu = &engine->pmu;
362362
bool busy;
@@ -391,6 +391,31 @@ static void engine_sample(struct intel_engine_cs *engine, unsigned int period_ns
391391
add_sample(&pmu->sample[I915_SAMPLE_BUSY], period_ns);
392392
}
393393

394+
static void gen2_engine_sample(struct intel_engine_cs *engine, unsigned int period_ns)
395+
{
396+
struct intel_engine_pmu *pmu = &engine->pmu;
397+
u32 tail, head, acthd;
398+
399+
tail = ENGINE_READ_FW(engine, RING_TAIL);
400+
head = ENGINE_READ_FW(engine, RING_HEAD);
401+
acthd = ENGINE_READ_FW(engine, ACTHD);
402+
403+
if (head & HEAD_WAIT_I8XX)
404+
add_sample(&pmu->sample[I915_SAMPLE_WAIT], period_ns);
405+
406+
if (head & HEAD_WAIT_I8XX || head != acthd ||
407+
(head & HEAD_ADDR) != (tail & TAIL_ADDR))
408+
add_sample(&pmu->sample[I915_SAMPLE_BUSY], period_ns);
409+
}
410+
411+
static void engine_sample(struct intel_engine_cs *engine, unsigned int period_ns)
412+
{
413+
if (GRAPHICS_VER(engine->i915) >= 3)
414+
gen3_engine_sample(engine, period_ns);
415+
else
416+
gen2_engine_sample(engine, period_ns);
417+
}
418+
394419
static void
395420
engines_sample(struct intel_gt *gt, unsigned int period_ns)
396421
{
@@ -834,15 +859,14 @@ static void i915_pmu_event_start(struct perf_event *event, int flags)
834859

835860
static void i915_pmu_event_stop(struct perf_event *event, int flags)
836861
{
837-
struct drm_i915_private *i915 =
838-
container_of(event->pmu, typeof(*i915), pmu.base);
839-
struct i915_pmu *pmu = &i915->pmu;
862+
struct i915_pmu *pmu = event_to_pmu(event);
840863

841864
if (pmu->closed)
842865
goto out;
843866

844867
if (flags & PERF_EF_UPDATE)
845868
i915_pmu_event_read(event);
869+
846870
i915_pmu_disable(event);
847871

848872
out:
@@ -1232,17 +1256,6 @@ static void i915_pmu_unregister_cpuhp_state(struct i915_pmu *pmu)
12321256
cpuhp_state_remove_instance(cpuhp_slot, &pmu->cpuhp.node);
12331257
}
12341258

1235-
static bool is_igp(struct drm_i915_private *i915)
1236-
{
1237-
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
1238-
1239-
/* IGP is 0000:00:02.0 */
1240-
return pci_domain_nr(pdev->bus) == 0 &&
1241-
pdev->bus->number == 0 &&
1242-
PCI_SLOT(pdev->devfn) == 2 &&
1243-
PCI_FUNC(pdev->devfn) == 0;
1244-
}
1245-
12461259
void i915_pmu_register(struct drm_i915_private *i915)
12471260
{
12481261
struct i915_pmu *pmu = &i915->pmu;
@@ -1255,18 +1268,13 @@ void i915_pmu_register(struct drm_i915_private *i915)
12551268

12561269
int ret = -ENOMEM;
12571270

1258-
if (GRAPHICS_VER(i915) <= 2) {
1259-
drm_info(&i915->drm, "PMU not supported for this GPU.");
1260-
return;
1261-
}
1262-
12631271
spin_lock_init(&pmu->lock);
12641272
hrtimer_init(&pmu->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
12651273
pmu->timer.function = i915_sample;
12661274
pmu->cpuhp.cpu = -1;
12671275
init_rc6(pmu);
12681276

1269-
if (!is_igp(i915)) {
1277+
if (IS_DGFX(i915)) {
12701278
pmu->name = kasprintf(GFP_KERNEL,
12711279
"i915_%s",
12721280
dev_name(i915->drm.dev));
@@ -1318,7 +1326,7 @@ void i915_pmu_register(struct drm_i915_private *i915)
13181326
pmu->base.event_init = NULL;
13191327
free_event_attributes(pmu);
13201328
err_name:
1321-
if (!is_igp(i915))
1329+
if (IS_DGFX(i915))
13221330
kfree(pmu->name);
13231331
err:
13241332
drm_notice(&i915->drm, "Failed to register PMU!\n");
@@ -1346,7 +1354,7 @@ void i915_pmu_unregister(struct drm_i915_private *i915)
13461354
perf_pmu_unregister(&pmu->base);
13471355
pmu->base.event_init = NULL;
13481356
kfree(pmu->base.attr_groups);
1349-
if (!is_igp(i915))
1357+
if (IS_DGFX(i915))
13501358
kfree(pmu->name);
13511359
free_event_attributes(pmu);
13521360
}

‎drivers/gpu/drm/i915/pxp/intel_pxp.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -170,7 +170,7 @@ static struct intel_gt *find_gt_for_required_teelink(struct drm_i915_private *i9
170170

171171
static struct intel_gt *find_gt_for_required_protected_content(struct drm_i915_private *i915)
172172
{
173-
if (!IS_ENABLED(CONFIG_DRM_I915_PXP) || !INTEL_INFO(i915)->has_pxp)
173+
if (!HAS_PXP(i915))
174174
return NULL;
175175

176176
/*

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