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airliedairlied
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Merge tag 'amd-drm-fixes-6.15-2025-04-16' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-6.15-2025-04-16: amdgpu: - Cleaner shader sysfs fix - Suspend fix - Fix doorbell free ordering - Video caps fix - DML2 memory allocation optimization - HDP fix Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://lore.kernel.org/r/20250416223137.1146653-1-alexander.deucher@amd.com
2 parents 8ffd015 + c235a71 commit c925e99

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17 files changed

+66
-35
lines changed

17 files changed

+66
-35
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1123,6 +1123,7 @@ struct amdgpu_device {
11231123
bool in_s3;
11241124
bool in_s4;
11251125
bool in_s0ix;
1126+
suspend_state_t last_suspend_state;
11261127

11271128
enum pp_mp1_state mp1_state;
11281129
struct amdgpu_doorbell_index doorbell_index;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3510,6 +3510,7 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
35103510
amdgpu_device_mem_scratch_fini(adev);
35113511
amdgpu_ib_pool_fini(adev);
35123512
amdgpu_seq64_fini(adev);
3513+
amdgpu_doorbell_fini(adev);
35133514
}
35143515
if (adev->ip_blocks[i].version->funcs->sw_fini) {
35153516
r = adev->ip_blocks[i].version->funcs->sw_fini(&adev->ip_blocks[i]);
@@ -4858,7 +4859,6 @@ void amdgpu_device_fini_sw(struct amdgpu_device *adev)
48584859

48594860
iounmap(adev->rmmio);
48604861
adev->rmmio = NULL;
4861-
amdgpu_doorbell_fini(adev);
48624862
drm_dev_exit(idx);
48634863
}
48644864

‎drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2548,8 +2548,20 @@ static int amdgpu_pmops_suspend(struct device *dev)
25482548
adev->in_s0ix = true;
25492549
else if (amdgpu_acpi_is_s3_active(adev))
25502550
adev->in_s3 = true;
2551-
if (!adev->in_s0ix && !adev->in_s3)
2551+
if (!adev->in_s0ix && !adev->in_s3) {
2552+
/* don't allow going deep first time followed by s2idle the next time */
2553+
if (adev->last_suspend_state != PM_SUSPEND_ON &&
2554+
adev->last_suspend_state != pm_suspend_target_state) {
2555+
drm_err_once(drm_dev, "Unsupported suspend state %d\n",
2556+
pm_suspend_target_state);
2557+
return -EINVAL;
2558+
}
25522559
return 0;
2560+
}
2561+
2562+
/* cache the state last used for suspend */
2563+
adev->last_suspend_state = pm_suspend_target_state;
2564+
25532565
return amdgpu_device_suspend(drm_dev, true);
25542566
}
25552567

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1438,9 +1438,11 @@ static int amdgpu_gfx_run_cleaner_shader_job(struct amdgpu_ring *ring)
14381438
struct amdgpu_device *adev = ring->adev;
14391439
struct drm_gpu_scheduler *sched = &ring->sched;
14401440
struct drm_sched_entity entity;
1441+
static atomic_t counter;
14411442
struct dma_fence *f;
14421443
struct amdgpu_job *job;
14431444
struct amdgpu_ib *ib;
1445+
void *owner;
14441446
int i, r;
14451447

14461448
/* Initialize the scheduler entity */
@@ -1451,9 +1453,15 @@ static int amdgpu_gfx_run_cleaner_shader_job(struct amdgpu_ring *ring)
14511453
goto err;
14521454
}
14531455

1454-
r = amdgpu_job_alloc_with_ib(ring->adev, &entity, NULL,
1455-
64, 0,
1456-
&job);
1456+
/*
1457+
* Use some unique dummy value as the owner to make sure we execute
1458+
* the cleaner shader on each submission. The value just need to change
1459+
* for each submission and is otherwise meaningless.
1460+
*/
1461+
owner = (void *)(unsigned long)atomic_inc_return(&counter);
1462+
1463+
r = amdgpu_job_alloc_with_ib(ring->adev, &entity, owner,
1464+
64, 0, &job);
14571465
if (r)
14581466
goto err;
14591467

‎drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -6114,7 +6114,7 @@ static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
61146114
}
61156115

61166116
if (amdgpu_emu_mode == 1)
6117-
adev->hdp.funcs->flush_hdp(adev, NULL);
6117+
amdgpu_device_flush_hdp(adev, NULL);
61186118

61196119
tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
61206120
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
@@ -6192,7 +6192,7 @@ static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
61926192
}
61936193

61946194
if (amdgpu_emu_mode == 1)
6195-
adev->hdp.funcs->flush_hdp(adev, NULL);
6195+
amdgpu_device_flush_hdp(adev, NULL);
61966196

61976197
tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
61986198
tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
@@ -6269,7 +6269,7 @@ static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
62696269
}
62706270

62716271
if (amdgpu_emu_mode == 1)
6272-
adev->hdp.funcs->flush_hdp(adev, NULL);
6272+
amdgpu_device_flush_hdp(adev, NULL);
62736273

62746274
tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
62756275
tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
@@ -6644,7 +6644,7 @@ static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
66446644
}
66456645

66466646
if (amdgpu_emu_mode == 1)
6647-
adev->hdp.funcs->flush_hdp(adev, NULL);
6647+
amdgpu_device_flush_hdp(adev, NULL);
66486648

66496649
tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
66506650
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);

‎drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2428,7 +2428,7 @@ static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr)
24282428
}
24292429

24302430
if (amdgpu_emu_mode == 1)
2431-
adev->hdp.funcs->flush_hdp(adev, NULL);
2431+
amdgpu_device_flush_hdp(adev, NULL);
24322432

24332433
tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
24342434
tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
@@ -2472,7 +2472,7 @@ static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr)
24722472
}
24732473

24742474
if (amdgpu_emu_mode == 1)
2475-
adev->hdp.funcs->flush_hdp(adev, NULL);
2475+
amdgpu_device_flush_hdp(adev, NULL);
24762476

24772477
tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
24782478
tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
@@ -2517,7 +2517,7 @@ static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr)
25172517
}
25182518

25192519
if (amdgpu_emu_mode == 1)
2520-
adev->hdp.funcs->flush_hdp(adev, NULL);
2520+
amdgpu_device_flush_hdp(adev, NULL);
25212521

25222522
tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
25232523
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
@@ -3153,7 +3153,7 @@ static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev)
31533153
amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj);
31543154

31553155
if (amdgpu_emu_mode == 1)
3156-
adev->hdp.funcs->flush_hdp(adev, NULL);
3156+
amdgpu_device_flush_hdp(adev, NULL);
31573157

31583158
WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
31593159
lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
@@ -3371,7 +3371,7 @@ static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev)
33713371
amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj);
33723372

33733373
if (amdgpu_emu_mode == 1)
3374-
adev->hdp.funcs->flush_hdp(adev, NULL);
3374+
amdgpu_device_flush_hdp(adev, NULL);
33753375

33763376
WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
33773377
lower_32_bits(adev->gfx.me.me_fw_gpu_addr));
@@ -4541,7 +4541,7 @@ static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev)
45414541
if (r)
45424542
return r;
45434543

4544-
adev->hdp.funcs->flush_hdp(adev, NULL);
4544+
amdgpu_device_flush_hdp(adev, NULL);
45454545

45464546
value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
45474547
false : true;

‎drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2324,7 +2324,7 @@ static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev)
23242324
amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj);
23252325

23262326
if (amdgpu_emu_mode == 1)
2327-
adev->hdp.funcs->flush_hdp(adev, NULL);
2327+
amdgpu_device_flush_hdp(adev, NULL);
23282328

23292329
WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
23302330
lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
@@ -2468,7 +2468,7 @@ static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev)
24682468
amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj);
24692469

24702470
if (amdgpu_emu_mode == 1)
2471-
adev->hdp.funcs->flush_hdp(adev, NULL);
2471+
amdgpu_device_flush_hdp(adev, NULL);
24722472

24732473
WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
24742474
lower_32_bits(adev->gfx.me.me_fw_gpu_addr));
@@ -3426,7 +3426,7 @@ static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev)
34263426
if (r)
34273427
return r;
34283428

3429-
adev->hdp.funcs->flush_hdp(adev, NULL);
3429+
amdgpu_device_flush_hdp(adev, NULL);
34303430

34313431
value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
34323432
false : true;

‎drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -268,7 +268,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
268268
ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
269269

270270
/* flush hdp cache */
271-
adev->hdp.funcs->flush_hdp(adev, NULL);
271+
amdgpu_device_flush_hdp(adev, NULL);
272272

273273
/* This is necessary for SRIOV as well as for GFXOFF to function
274274
* properly under bare metal
@@ -969,7 +969,7 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
969969
adev->hdp.funcs->init_registers(adev);
970970

971971
/* Flush HDP after it is initialized */
972-
adev->hdp.funcs->flush_hdp(adev, NULL);
972+
amdgpu_device_flush_hdp(adev, NULL);
973973

974974
value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
975975
false : true;

‎drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -229,7 +229,7 @@ static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
229229
ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
230230

231231
/* flush hdp cache */
232-
adev->hdp.funcs->flush_hdp(adev, NULL);
232+
amdgpu_device_flush_hdp(adev, NULL);
233233

234234
/* This is necessary for SRIOV as well as for GFXOFF to function
235235
* properly under bare metal
@@ -899,7 +899,7 @@ static int gmc_v11_0_gart_enable(struct amdgpu_device *adev)
899899
return r;
900900

901901
/* Flush HDP after it is initialized */
902-
adev->hdp.funcs->flush_hdp(adev, NULL);
902+
amdgpu_device_flush_hdp(adev, NULL);
903903

904904
value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
905905
false : true;

‎drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -297,7 +297,7 @@ static void gmc_v12_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
297297
return;
298298

299299
/* flush hdp cache */
300-
adev->hdp.funcs->flush_hdp(adev, NULL);
300+
amdgpu_device_flush_hdp(adev, NULL);
301301

302302
/* This is necessary for SRIOV as well as for GFXOFF to function
303303
* properly under bare metal
@@ -881,7 +881,7 @@ static int gmc_v12_0_gart_enable(struct amdgpu_device *adev)
881881
return r;
882882

883883
/* Flush HDP after it is initialized */
884-
adev->hdp.funcs->flush_hdp(adev, NULL);
884+
amdgpu_device_flush_hdp(adev, NULL);
885885

886886
value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
887887
false : true;

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