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Merge tag 'drm-fixes-2024-12-06' of https://gitlab.freedesktop.org/drm/kernel
Pull more drm fixes from Simona Vetter: "Due to mailing list unreliability we missed the amdgpu pull, hence part two with that now included: - amdgu: mostly display fixes + jpeg vcn 1.0, sriov, dcn4.0 resume fixes - amdkfd fixes" * tag 'drm-fixes-2024-12-06' of https://gitlab.freedesktop.org/drm/kernel: drm/amdgpu: rework resume handling for display (v2) drm/amd/pm: fix and simplify workload handling Revert "drm/amd/pm: correct the workload setting" drm/amdgpu: fix sriov reinit late orders drm/amdgpu: Fix ISP hw init issue drm/amd/display: Add hblank borrowing support drm/amd/display: Limit VTotal range to max hw cap minus fp drm/amd/display: Correct prefetch calculation drm/amd/display: Add option to retrieve detile buffer size drm/amd/display: Add a left edge pixel if in YCbCr422 or YCbCr420 and odm drm/amdkfd: hard-code cacheline for gc943,gc944 drm/amdkfd: add MEC version that supports no PCIe atomics for GFX12 drm/amd/display: Fix programming backlight on OLED panels drm/amd: Sanity check the ACPI EDID drm/amdgpu/hdp7.0: do a posting read when flushing HDP drm/amdgpu/hdp6.0: do a posting read when flushing HDP drm/amdgpu/hdp5.2: do a posting read when flushing HDP drm/amdgpu/hdp5.0: do a posting read when flushing HDP drm/amdgpu/hdp4.0: do a posting read when flushing HDP drm/amdgpu/jpeg1.0: fix idle work handler
2 parents 9a6e8c7 + 1995e7d commit c7cde62

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49 files changed

+1031
-615
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

Lines changed: 64 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -145,7 +145,7 @@ const char *amdgpu_asic_name[] = {
145145
"LAST",
146146
};
147147

148-
#define AMDGPU_IP_BLK_MASK_ALL GENMASK(AMDGPU_MAX_IP_NUM - 1, 0)
148+
#define AMDGPU_IP_BLK_MASK_ALL GENMASK(AMDGPU_MAX_IP_NUM, 0)
149149
/*
150150
* Default init level where all blocks are expected to be initialized. This is
151151
* the level of initialization expected by default and also after a full reset
@@ -3670,9 +3670,11 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
36703670
continue;
36713671

36723672
r = block->version->funcs->hw_init(&adev->ip_blocks[i]);
3673-
DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
3674-
if (r)
3673+
if (r) {
3674+
dev_err(adev->dev, "RE-INIT-early: %s failed\n",
3675+
block->version->funcs->name);
36753676
return r;
3677+
}
36763678
block->status.hw = true;
36773679
}
36783680
}
@@ -3682,7 +3684,8 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
36823684

36833685
static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
36843686
{
3685-
int i, r;
3687+
struct amdgpu_ip_block *block;
3688+
int i, r = 0;
36863689

36873690
static enum amd_ip_block_type ip_order[] = {
36883691
AMD_IP_BLOCK_TYPE_SMC,
@@ -3697,34 +3700,28 @@ static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
36973700
};
36983701

36993702
for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
3700-
int j;
3701-
struct amdgpu_ip_block *block;
3702-
3703-
for (j = 0; j < adev->num_ip_blocks; j++) {
3704-
block = &adev->ip_blocks[j];
3703+
block = amdgpu_device_ip_get_ip_block(adev, ip_order[i]);
37053704

3706-
if (block->version->type != ip_order[i] ||
3707-
!block->status.valid ||
3708-
block->status.hw)
3709-
continue;
3705+
if (!block)
3706+
continue;
37103707

3708+
if (block->status.valid && !block->status.hw) {
37113709
if (block->version->type == AMD_IP_BLOCK_TYPE_SMC) {
3712-
r = amdgpu_ip_block_resume(&adev->ip_blocks[i]);
3713-
if (r)
3714-
return r;
3710+
r = amdgpu_ip_block_resume(block);
37153711
} else {
3716-
r = block->version->funcs->hw_init(&adev->ip_blocks[i]);
3717-
if (r) {
3718-
DRM_ERROR("hw_init of IP block <%s> failed %d\n",
3719-
adev->ip_blocks[i].version->funcs->name, r);
3720-
return r;
3721-
}
3722-
block->status.hw = true;
3712+
r = block->version->funcs->hw_init(block);
37233713
}
3714+
3715+
if (r) {
3716+
dev_err(adev->dev, "RE-INIT-late: %s failed\n",
3717+
block->version->funcs->name);
3718+
break;
3719+
}
3720+
block->status.hw = true;
37243721
}
37253722
}
37263723

3727-
return 0;
3724+
return r;
37283725
}
37293726

37303727
/**
@@ -3765,7 +3762,7 @@ static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
37653762
*
37663763
* @adev: amdgpu_device pointer
37673764
*
3768-
* First resume function for hardware IPs. The list of all the hardware
3765+
* Second resume function for hardware IPs. The list of all the hardware
37693766
* IPs that make up the asic is walked and the resume callbacks are run for
37703767
* all blocks except COMMON, GMC, and IH. resume puts the hardware into a
37713768
* functional state after a suspend and updates the software state as
@@ -3783,6 +3780,7 @@ static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
37833780
if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
37843781
adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
37853782
adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3783+
adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE ||
37863784
adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
37873785
continue;
37883786
r = amdgpu_ip_block_resume(&adev->ip_blocks[i]);
@@ -3793,6 +3791,36 @@ static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
37933791
return 0;
37943792
}
37953793

3794+
/**
3795+
* amdgpu_device_ip_resume_phase3 - run resume for hardware IPs
3796+
*
3797+
* @adev: amdgpu_device pointer
3798+
*
3799+
* Third resume function for hardware IPs. The list of all the hardware
3800+
* IPs that make up the asic is walked and the resume callbacks are run for
3801+
* all DCE. resume puts the hardware into a functional state after a suspend
3802+
* and updates the software state as necessary. This function is also used
3803+
* for restoring the GPU after a GPU reset.
3804+
*
3805+
* Returns 0 on success, negative error code on failure.
3806+
*/
3807+
static int amdgpu_device_ip_resume_phase3(struct amdgpu_device *adev)
3808+
{
3809+
int i, r;
3810+
3811+
for (i = 0; i < adev->num_ip_blocks; i++) {
3812+
if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3813+
continue;
3814+
if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) {
3815+
r = amdgpu_ip_block_resume(&adev->ip_blocks[i]);
3816+
if (r)
3817+
return r;
3818+
}
3819+
}
3820+
3821+
return 0;
3822+
}
3823+
37963824
/**
37973825
* amdgpu_device_ip_resume - run resume for hardware IPs
37983826
*
@@ -3822,6 +3850,13 @@ static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
38223850
if (adev->mman.buffer_funcs_ring->sched.ready)
38233851
amdgpu_ttm_set_buffer_funcs_status(adev, true);
38243852

3853+
if (r)
3854+
return r;
3855+
3856+
amdgpu_fence_driver_hw_init(adev);
3857+
3858+
r = amdgpu_device_ip_resume_phase3(adev);
3859+
38253860
return r;
38263861
}
38273862

@@ -4902,7 +4937,6 @@ int amdgpu_device_resume(struct drm_device *dev, bool notify_clients)
49024937
dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r);
49034938
goto exit;
49044939
}
4905-
amdgpu_fence_driver_hw_init(adev);
49064940

49074941
if (!adev->in_s0ix) {
49084942
r = amdgpu_amdkfd_resume(adev, adev->in_runpm);
@@ -5487,6 +5521,10 @@ int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context)
54875521
if (tmp_adev->mman.buffer_funcs_ring->sched.ready)
54885522
amdgpu_ttm_set_buffer_funcs_status(tmp_adev, true);
54895523

5524+
r = amdgpu_device_ip_resume_phase3(tmp_adev);
5525+
if (r)
5526+
goto out;
5527+
54905528
if (vram_lost)
54915529
amdgpu_device_fill_reset_magic(tmp_adev);
54925530

‎drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -40,10 +40,12 @@
4040
static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
4141
struct amdgpu_ring *ring)
4242
{
43-
if (!ring || !ring->funcs->emit_wreg)
43+
if (!ring || !ring->funcs->emit_wreg) {
4444
WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
45-
else
45+
RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
46+
} else {
4647
amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
48+
}
4749
}
4850

4951
static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
@@ -54,11 +56,13 @@ static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
5456
amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 5))
5557
return;
5658

57-
if (!ring || !ring->funcs->emit_wreg)
59+
if (!ring || !ring->funcs->emit_wreg) {
5860
WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
59-
else
61+
RREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE);
62+
} else {
6063
amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
6164
HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
65+
}
6266
}
6367

6468
static void hdp_v4_0_query_ras_error_count(struct amdgpu_device *adev,

‎drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -31,17 +31,20 @@
3131
static void hdp_v5_0_flush_hdp(struct amdgpu_device *adev,
3232
struct amdgpu_ring *ring)
3333
{
34-
if (!ring || !ring->funcs->emit_wreg)
34+
if (!ring || !ring->funcs->emit_wreg) {
3535
WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
36-
else
36+
RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
37+
} else {
3738
amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
39+
}
3840
}
3941

4042
static void hdp_v5_0_invalidate_hdp(struct amdgpu_device *adev,
4143
struct amdgpu_ring *ring)
4244
{
4345
if (!ring || !ring->funcs->emit_wreg) {
4446
WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
47+
RREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE);
4548
} else {
4649
amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
4750
HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);

‎drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -31,13 +31,15 @@
3131
static void hdp_v5_2_flush_hdp(struct amdgpu_device *adev,
3232
struct amdgpu_ring *ring)
3333
{
34-
if (!ring || !ring->funcs->emit_wreg)
34+
if (!ring || !ring->funcs->emit_wreg) {
3535
WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2,
3636
0);
37-
else
37+
RREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
38+
} else {
3839
amdgpu_ring_emit_wreg(ring,
3940
(adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2,
4041
0);
42+
}
4143
}
4244

4345
static void hdp_v5_2_update_mem_power_gating(struct amdgpu_device *adev,

‎drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -34,10 +34,12 @@
3434
static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev,
3535
struct amdgpu_ring *ring)
3636
{
37-
if (!ring || !ring->funcs->emit_wreg)
37+
if (!ring || !ring->funcs->emit_wreg) {
3838
WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
39-
else
39+
RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
40+
} else {
4041
amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
42+
}
4143
}
4244

4345
static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev,

‎drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -31,10 +31,12 @@
3131
static void hdp_v7_0_flush_hdp(struct amdgpu_device *adev,
3232
struct amdgpu_ring *ring)
3333
{
34-
if (!ring || !ring->funcs->emit_wreg)
34+
if (!ring || !ring->funcs->emit_wreg) {
3535
WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
36-
else
36+
RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
37+
} else {
3738
amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
39+
}
3840
}
3941

4042
static void hdp_v7_0_update_clock_gating(struct amdgpu_device *adev,

‎drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -604,7 +604,7 @@ static void jpeg_v1_0_set_irq_funcs(struct amdgpu_device *adev)
604604
static void jpeg_v1_0_ring_begin_use(struct amdgpu_ring *ring)
605605
{
606606
struct amdgpu_device *adev = ring->adev;
607-
bool set_clocks = !cancel_delayed_work_sync(&adev->jpeg.idle_work);
607+
bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
608608
int cnt = 0;
609609

610610
mutex_lock(&adev->vcn.vcn1_jpeg1_workaround);

‎drivers/gpu/drm/amd/amdkfd/kfd_crat.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1510,6 +1510,8 @@ static int kfd_fill_gpu_cache_info_from_gfx_config_v2(struct kfd_dev *kdev,
15101510
if (adev->gfx.config.gc_tcp_size_per_cu) {
15111511
pcache_info[i].cache_size = adev->gfx.config.gc_tcp_size_per_cu;
15121512
pcache_info[i].cache_level = 1;
1513+
/* Cacheline size not available in IP discovery for gc943,gc944 */
1514+
pcache_info[i].cache_line_size = 128;
15131515
pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
15141516
CRAT_CACHE_FLAGS_DATA_CACHE |
15151517
CRAT_CACHE_FLAGS_SIMD_CACHE);
@@ -1521,6 +1523,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config_v2(struct kfd_dev *kdev,
15211523
pcache_info[i].cache_size =
15221524
adev->gfx.config.gc_l1_instruction_cache_size_per_sqc;
15231525
pcache_info[i].cache_level = 1;
1526+
pcache_info[i].cache_line_size = 64;
15241527
pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
15251528
CRAT_CACHE_FLAGS_INST_CACHE |
15261529
CRAT_CACHE_FLAGS_SIMD_CACHE);
@@ -1531,6 +1534,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config_v2(struct kfd_dev *kdev,
15311534
if (adev->gfx.config.gc_l1_data_cache_size_per_sqc) {
15321535
pcache_info[i].cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc;
15331536
pcache_info[i].cache_level = 1;
1537+
pcache_info[i].cache_line_size = 64;
15341538
pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
15351539
CRAT_CACHE_FLAGS_DATA_CACHE |
15361540
CRAT_CACHE_FLAGS_SIMD_CACHE);
@@ -1541,6 +1545,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config_v2(struct kfd_dev *kdev,
15411545
if (adev->gfx.config.gc_tcc_size) {
15421546
pcache_info[i].cache_size = adev->gfx.config.gc_tcc_size;
15431547
pcache_info[i].cache_level = 2;
1548+
pcache_info[i].cache_line_size = 128;
15441549
pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
15451550
CRAT_CACHE_FLAGS_DATA_CACHE |
15461551
CRAT_CACHE_FLAGS_SIMD_CACHE);
@@ -1551,6 +1556,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config_v2(struct kfd_dev *kdev,
15511556
if (adev->gmc.mall_size) {
15521557
pcache_info[i].cache_size = adev->gmc.mall_size / 1024;
15531558
pcache_info[i].cache_level = 3;
1559+
pcache_info[i].cache_line_size = 64;
15541560
pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
15551561
CRAT_CACHE_FLAGS_DATA_CACHE |
15561562
CRAT_CACHE_FLAGS_SIMD_CACHE);

‎drivers/gpu/drm/amd/amdkfd/kfd_device.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -235,6 +235,9 @@ static void kfd_device_info_init(struct kfd_dev *kfd,
235235
*/
236236
kfd->device_info.needs_pci_atomics = true;
237237
kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0;
238+
} else if (gc_version < IP_VERSION(13, 0, 0)) {
239+
kfd->device_info.needs_pci_atomics = true;
240+
kfd->device_info.no_atomic_fw_version = 2090;
238241
} else {
239242
kfd->device_info.needs_pci_atomics = true;
240243
}

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3481,6 +3481,8 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
34813481
caps->aux_support = false;
34823482
else if (amdgpu_backlight == 1)
34833483
caps->aux_support = true;
3484+
if (caps->aux_support)
3485+
aconnector->dc_link->backlight_control_type = BACKLIGHT_CONTROL_AMD_AUX;
34843486

34853487
luminance_range = &conn_base->display_info.luminance_range;
34863488

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