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claudiubezneageertu
claudiubeznea
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geertu
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pinctrl: renesas: rzg2l: Add RZ/G3S support
Add basic support for RZ/G3S to be able to boot from SD card, have a running console port, and use GPIOs. RZ/G3S has 82 general-purpose IO ports. Support for the remaining pin functions (e.g. Ethernet, XSPI) will be added along with controller-specific support. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230929053915.1530607-22-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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‎drivers/pinctrl/renesas/pinctrl-rzg2l.c

Lines changed: 124 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -58,13 +58,19 @@
5858
#define PIN_CFG_IOLH_C BIT(13)
5959
#define PIN_CFG_SOFT_PS BIT(14)
6060

61-
#define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \
62-
PIN_CFG_SR | \
61+
#define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \
62+
(PIN_CFG_IOLH_##group | \
6363
PIN_CFG_PUPD | \
6464
PIN_CFG_FILONOFF | \
6565
PIN_CFG_FILNUM | \
6666
PIN_CFG_FILCLKSEL)
6767

68+
#define RZG2L_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \
69+
PIN_CFG_SR)
70+
71+
#define RZG3S_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \
72+
PIN_CFG_SOFT_PS)
73+
6874
#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \
6975
PIN_CFG_FILONOFF | \
7076
PIN_CFG_FILNUM | \
@@ -1314,6 +1320,36 @@ static const u32 r9a07g043_gpio_configs[] = {
13141320
RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
13151321
};
13161322

1323+
static const u32 r9a08g045_gpio_configs[] = {
1324+
RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */
1325+
RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1326+
PIN_CFG_IO_VMC_ETH0)), /* P1 */
1327+
RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1328+
PIN_CFG_IO_VMC_ETH0)), /* P2 */
1329+
RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1330+
PIN_CFG_IO_VMC_ETH0)), /* P3 */
1331+
RZG2L_GPIO_PORT_PACK(6, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1332+
PIN_CFG_IO_VMC_ETH0)), /* P4 */
1333+
RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)), /* P5 */
1334+
RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */
1335+
RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1336+
PIN_CFG_IO_VMC_ETH1)), /* P7 */
1337+
RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1338+
PIN_CFG_IO_VMC_ETH1)), /* P8 */
1339+
RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1340+
PIN_CFG_IO_VMC_ETH1)), /* P9 */
1341+
RZG2L_GPIO_PORT_PACK(5, 0x37, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1342+
PIN_CFG_IO_VMC_ETH1)), /* P10 */
1343+
RZG2L_GPIO_PORT_PACK(4, 0x23, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P11 */
1344+
RZG2L_GPIO_PORT_PACK(2, 0x24, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P12 */
1345+
RZG2L_GPIO_PORT_PACK(5, 0x25, RZG3S_MPXED_PIN_FUNCS(A)), /* P13 */
1346+
RZG2L_GPIO_PORT_PACK(3, 0x26, RZG3S_MPXED_PIN_FUNCS(A)), /* P14 */
1347+
RZG2L_GPIO_PORT_PACK(4, 0x27, RZG3S_MPXED_PIN_FUNCS(A)), /* P15 */
1348+
RZG2L_GPIO_PORT_PACK(2, 0x28, RZG3S_MPXED_PIN_FUNCS(A)), /* P16 */
1349+
RZG2L_GPIO_PORT_PACK(4, 0x29, RZG3S_MPXED_PIN_FUNCS(A)), /* P17 */
1350+
RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */
1351+
};
1352+
13171353
static const struct {
13181354
struct rzg2l_dedicated_configs common[35];
13191355
struct rzg2l_dedicated_configs rzg2l_pins[7];
@@ -1400,6 +1436,46 @@ static const struct {
14001436
}
14011437
};
14021438

1439+
static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
1440+
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM |
1441+
PIN_CFG_FILCLKSEL)) },
1442+
{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN |
1443+
PIN_CFG_SOFT_PS)) },
1444+
{ "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) },
1445+
{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) },
1446+
{ "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
1447+
{ "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1448+
PIN_CFG_IO_VMC_SD0)) },
1449+
{ "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
1450+
{ "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1451+
PIN_CFG_IO_VMC_SD0)) },
1452+
{ "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1453+
PIN_CFG_IO_VMC_SD0)) },
1454+
{ "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1455+
PIN_CFG_IO_VMC_SD0)) },
1456+
{ "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1457+
PIN_CFG_IO_VMC_SD0)) },
1458+
{ "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1459+
PIN_CFG_IO_VMC_SD0)) },
1460+
{ "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1461+
PIN_CFG_IO_VMC_SD0)) },
1462+
{ "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1463+
PIN_CFG_IO_VMC_SD0)) },
1464+
{ "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1465+
PIN_CFG_IO_VMC_SD0)) },
1466+
{ "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD1)) },
1467+
{ "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1468+
PIN_CFG_IO_VMC_SD1)) },
1469+
{ "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1470+
PIN_CFG_IO_VMC_SD1)) },
1471+
{ "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1472+
PIN_CFG_IO_VMC_SD1)) },
1473+
{ "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1474+
PIN_CFG_IO_VMC_SD1)) },
1475+
{ "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1476+
PIN_CFG_IO_VMC_SD1)) },
1477+
};
1478+
14031479
static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data)
14041480
{
14051481
unsigned int gpioint;
@@ -1761,6 +1837,9 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
17611837
BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT >
17621838
ARRAY_SIZE(rzg2l_gpio_names));
17631839

1840+
BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT >
1841+
ARRAY_SIZE(rzg2l_gpio_names));
1842+
17641843
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
17651844
if (!pctrl)
17661845
return -ENOMEM;
@@ -1806,6 +1885,35 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = {
18061885
.iolh_groupb_oi = { 100, 66, 50, 33, },
18071886
};
18081887

1888+
static const struct rzg2l_hwcfg rzg3s_hwcfg = {
1889+
.regs = {
1890+
.pwpr = 0x3000,
1891+
.sd_ch = 0x3004,
1892+
},
1893+
.iolh_groupa_ua = {
1894+
/* 1v8 power source */
1895+
[RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000,
1896+
/* 3v3 power source */
1897+
[RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000,
1898+
},
1899+
.iolh_groupb_ua = {
1900+
/* 1v8 power source */
1901+
[RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000,
1902+
/* 3v3 power source */
1903+
[RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000,
1904+
},
1905+
.iolh_groupc_ua = {
1906+
/* 1v8 power source */
1907+
[RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800,
1908+
/* 2v5 source */
1909+
[RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100,
1910+
/* 3v3 power source */
1911+
[RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050,
1912+
},
1913+
.drive_strength_ua = true,
1914+
.func_base = 1,
1915+
};
1916+
18091917
static struct rzg2l_pinctrl_data r9a07g043_data = {
18101918
.port_pins = rzg2l_gpio_names,
18111919
.port_pin_configs = r9a07g043_gpio_configs,
@@ -1827,6 +1935,16 @@ static struct rzg2l_pinctrl_data r9a07g044_data = {
18271935
.hwcfg = &rzg2l_hwcfg,
18281936
};
18291937

1938+
static struct rzg2l_pinctrl_data r9a08g045_data = {
1939+
.port_pins = rzg2l_gpio_names,
1940+
.port_pin_configs = r9a08g045_gpio_configs,
1941+
.n_ports = ARRAY_SIZE(r9a08g045_gpio_configs),
1942+
.dedicated_pins = rzg3s_dedicated_pins,
1943+
.n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT,
1944+
.n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins),
1945+
.hwcfg = &rzg3s_hwcfg,
1946+
};
1947+
18301948
static const struct of_device_id rzg2l_pinctrl_of_table[] = {
18311949
{
18321950
.compatible = "renesas,r9a07g043-pinctrl",
@@ -1836,6 +1954,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = {
18361954
.compatible = "renesas,r9a07g044-pinctrl",
18371955
.data = &r9a07g044_data,
18381956
},
1957+
{
1958+
.compatible = "renesas,r9a08g045-pinctrl",
1959+
.data = &r9a08g045_data,
1960+
},
18391961
{ /* sentinel */ }
18401962
};
18411963

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