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Merge tag 'phy-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull phy updates from Vinod Koul: "New Support - Samsung Exynos gs101 drd combo phy - Qualcomm SC8180x USB uniphy, IPQ9574 QMP PCIe phy - Airoha EN7581 PCIe phy - Freescale i.MX8Q HSIO SerDes phy - Starfive jh7110 dphy tx Updates: - Resume support for j721e-wiz driver - Updates to Exynos usbdrd driver - Support for optional power domains in g12a usb2-phy driver - Debugfs support and updates to zynqmp driver" * tag 'phy-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (56 commits) phy: airoha: Add dtime and Rx AEQ IO registers dt-bindings: phy: airoha: Add dtime and Rx AEQ IO registers dt-bindings: phy: rockchip-emmc-phy: Convert to dtschema dt-bindings: phy: qcom,qmp-usb: fix spelling error phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo phy (HS & SS) phy: exynos5-usbdrd: convert Vbus supplies to regulator_bulk phy: exynos5-usbdrd: convert (phy) register access clock to clk_bulk phy: exynos5-usbdrd: convert core clocks to clk_bulk phy: exynos5-usbdrd: support isolating HS and SS ports independently dt-bindings: phy: samsung,usb3-drd-phy: add gs101 compatible phy: core: Fix documentation of of_phy_get phy: starfive: Correct the dphy configure process phy: zynqmp: Add debugfs support phy: zynqmp: Take the phy mutex in xlate phy: zynqmp: Only wait for PLL lock "primary" instances phy: zynqmp: Store instance instead of type phy: zynqmp: Enable reference clock correctly phy: cadence-torrent: Check return value on register read phy: Fix the cacography in phy-exynos5250-usb2.c phy: phy-rockchip-samsung-hdptx: Select CONFIG_MFD_SYSCON ...
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‎Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/airoha,en7581-pcie-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Airoha EN7581 PCI-Express PHY
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maintainers:
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- Lorenzo Bianconi <lorenzo@kernel.org>
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description:
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The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port.
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properties:
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compatible:
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const: airoha,en7581-pcie-phy
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reg:
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items:
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- description: PCIE analog base address
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- description: PCIE lane0 base address
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- description: PCIE lane1 base address
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- description: PCIE lane0 detection time base address
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- description: PCIE lane1 detection time base address
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- description: PCIE Rx AEQ base address
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reg-names:
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items:
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- const: csr-2l
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- const: pma0
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- const: pma1
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- const: p0-xr-dtime
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- const: p1-xr-dtime
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- const: rx-aeq
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"#phy-cells":
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const: 0
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required:
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- compatible
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- reg
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- reg-names
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- "#phy-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/phy/phy.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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phy@11e80000 {
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compatible = "airoha,en7581-pcie-phy";
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#phy-cells = <0>;
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reg = <0x0 0x1fa5a000 0x0 0xfff>,
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<0x0 0x1fa5b000 0x0 0xfff>,
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<0x0 0x1fa5c000 0x0 0xfff>,
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<0x0 0x1fc10044 0x0 0x4>,
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<0x0 0x1fc30044 0x0 0x4>,
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<0x0 0x1fc15030 0x0 0x104>;
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reg-names = "csr-2l", "pma0", "pma1",
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"p0-xr-dtime", "p1-xr-dtime",
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"rx-aeq";
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};
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};

‎Documentation/devicetree/bindings/phy/amlogic,g12a-usb2-phy.yaml

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Phandle to a regulator that provides power to the PHY. This
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regulator will be managed during the PHY power on/off sequence.
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg

‎Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/fsl,imx8qm-hsio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX8QM SoC series High Speed IO(HSIO) SERDES PHY
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maintainers:
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- Richard Zhu <hongxing.zhu@nxp.com>
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properties:
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compatible:
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enum:
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- fsl,imx8qm-hsio
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- fsl,imx8qxp-hsio
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reg:
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items:
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- description: Base address and length of the PHY block
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- description: HSIO control and status registers(CSR) of the PHY
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- description: HSIO CSR of the controller bound to the PHY
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- description: HSIO CSR for MISC
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reg-names:
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items:
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- const: reg
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- const: phy
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- const: ctrl
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- const: misc
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"#phy-cells":
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const: 3
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description:
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The first defines lane index.
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The second defines the type of the PHY refer to the include phy.h.
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The third defines the controller index, indicated which controller
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is bound to the lane.
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clocks:
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minItems: 5
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maxItems: 14
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clock-names:
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minItems: 5
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maxItems: 14
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fsl,hsio-cfg:
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description: |
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Specifies the use case of the HSIO module in the hardware design.
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Regarding the design of i.MX8QM HSIO subsystem, HSIO module can be
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confiured as following three use cases.
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+---------------------------------------+
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| | i.MX8QM |
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|------------------|--------------------|
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| | Lane0| Lane1| Lane2|
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|------------------|------|------|------|
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| pciea-x2-sata | PCIEA| PCIEA| SATA |
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|------------------|------|------|------|
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| pciea-x2-pcieb | PCIEA| PCIEA| PCIEB|
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|------------------|------|------|------|
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| pciea-pcieb-sata | PCIEA| PCIEB| SATA |
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+---------------------------------------+
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$ref: /schemas/types.yaml#/definitions/string
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enum: [ pciea-x2-sata, pciea-x2-pcieb, pciea-pcieb-sata]
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default: pciea-pcieb-sata
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fsl,refclk-pad-mode:
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description:
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Specifies the mode of the refclk pad used. INPUT(PHY refclock is
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provided externally via the refclk pad) or OUTPUT(PHY refclock is
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derived from SoC internal source and provided on the refclk pad).
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This property not exists means unused(PHY refclock is derived from
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SoC internal source).
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$ref: /schemas/types.yaml#/definitions/string
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enum: [ input, output, unused ]
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default: unused
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power-domains:
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minItems: 1
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maxItems: 2
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required:
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- compatible
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- reg
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- reg-names
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- "#phy-cells"
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- clocks
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- clock-names
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- fsl,hsio-cfg
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8qxp-hsio
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then:
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properties:
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clock-names:
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items:
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- const: pclk0
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- const: apb_pclk0
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- const: phy0_crr
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- const: ctl0_crr
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- const: misc_crr
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power-domains:
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maxItems: 1
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8qm-hsio
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then:
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properties:
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clock-names:
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items:
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- const: pclk0
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- const: pclk1
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- const: apb_pclk0
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- const: apb_pclk1
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- const: pclk2
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- const: epcs_tx
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- const: epcs_rx
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- const: apb_pclk2
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- const: phy0_crr
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- const: phy1_crr
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- const: ctl0_crr
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- const: ctl1_crr
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- const: ctl2_crr
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- const: misc_crr
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power-domains:
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minItems: 2
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8-clock.h>
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#include <dt-bindings/clock/imx8-lpcg.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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phy@5f1a0000 {
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compatible = "fsl,imx8qxp-hsio";
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reg = <0x5f1a0000 0x10000>,
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<0x5f120000 0x10000>,
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<0x5f140000 0x10000>,
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<0x5f160000 0x10000>;
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reg-names = "reg", "phy", "ctrl", "misc";
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clocks = <&phyx1_lpcg IMX_LPCG_CLK_0>,
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<&phyx1_lpcg IMX_LPCG_CLK_4>,
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<&phyx1_crr1_lpcg IMX_LPCG_CLK_4>,
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<&pcieb_crr3_lpcg IMX_LPCG_CLK_4>,
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<&misc_crr5_lpcg IMX_LPCG_CLK_4>;
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clock-names = "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr", "misc_crr";
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power-domains = <&pd IMX_SC_R_SERDES_1>;
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#phy-cells = <3>;
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fsl,hsio-cfg = "pciea-pcieb-sata";
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fsl,refclk-pad-mode = "input";
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};
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...

‎Documentation/devicetree/bindings/phy/marvell,armada-cp110-utmi-phy.yaml

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Phandle to the system controller node
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$ref: /schemas/types.yaml#/definitions/phandle
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swap-dx-lanes:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description: |
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Specifies the ports which will swap the differential-pair (D+/D-),
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default is not-swapped.
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# Required child nodes:
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patternProperties:

‎Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml

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- qcom,ipq6018-qmp-pcie-phy
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- qcom,ipq8074-qmp-gen3-pcie-phy
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- qcom,ipq8074-qmp-pcie-phy
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- qcom,ipq9574-qmp-gen3x1-pcie-phy
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- qcom,ipq9574-qmp-gen3x2-pcie-phy
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reg:
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items:

‎Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml

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"#clock-cells": true
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clock-output-names:
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minItems: 1
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maxItems: 2
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maxItems: 1
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9796
"#phy-cells":
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const: 0
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- qcom,sm8650-qmp-gen4x2-pcie-phy
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then:
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properties:
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clock-output-names:
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minItems: 2
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"#clock-cells":
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const: 1
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else:
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properties:
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clock-output-names:
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maxItems: 1
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"#clock-cells":
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const: 0
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‎Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml

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- qcom,ipq8074-qmp-usb3-phy
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- qcom,ipq9574-qmp-usb3-phy
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- qcom,msm8996-qmp-usb3-phy
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- com,qdu1000-qmp-usb3-uni-phy
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- qcom,qdu1000-qmp-usb3-uni-phy
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- qcom,sa8775p-qmp-usb3-uni-phy
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- qcom,sc8180x-qmp-usb3-uni-phy
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- qcom,sc8280xp-qmp-usb3-uni-phy
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- qcom,sdm845-qmp-usb3-uni-phy
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- qcom,sdx55-qmp-usb3-uni-phy
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enum:
113114
- qcom,qdu1000-qmp-usb3-uni-phy
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- qcom,sa8775p-qmp-usb3-uni-phy
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- qcom,sc8180x-qmp-usb3-uni-phy
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- qcom,sc8280xp-qmp-usb3-uni-phy
116118
- qcom,sm8150-qmp-usb3-uni-phy
117119
- qcom,sm8250-qmp-usb3-uni-phy
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contains:
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enum:
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- qcom,sa8775p-qmp-usb3-uni-phy
157+
- qcom,sc8180x-qmp-usb3-uni-phy
155158
- qcom,sc8280xp-qmp-usb3-uni-phy
156159
- qcom,x1e80100-qmp-usb3-uni-phy
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then:

‎Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.yaml

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contains:
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enum:
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- qcom,usb-hs-phy-apq8064
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- qcom,usb-hs-phy-msm8660
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- qcom,usb-hs-phy-msm8960
1920
then:
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properties:
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- enum:
4243
- qcom,usb-hs-phy-apq8064
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- qcom,usb-hs-phy-msm8226
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- qcom,usb-hs-phy-msm8660
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- qcom,usb-hs-phy-msm8916
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- qcom,usb-hs-phy-msm8960
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- qcom,usb-hs-phy-msm8974

‎Documentation/devicetree/bindings/phy/rockchip,rk3399-emmc-phy.yaml

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# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/rockchip,rk3399-emmc-phy.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Rockchip EMMC PHY
8+
9+
maintainers:
10+
- Heiko Stuebner <heiko@sntech.de>
11+
12+
properties:
13+
compatible:
14+
const: rockchip,rk3399-emmc-phy
15+
16+
reg:
17+
maxItems: 1
18+
19+
clocks:
20+
maxItems: 1
21+
22+
clock-names:
23+
const: emmcclk
24+
25+
drive-impedance-ohm:
26+
$ref: /schemas/types.yaml#/definitions/uint32
27+
description:
28+
Specifies the drive impedance in Ohm.
29+
enum: [33, 40, 50, 66, 100]
30+
default: 50
31+
32+
rockchip,enable-strobe-pulldown:
33+
type: boolean
34+
description: |
35+
Enable internal pull-down for the strobe
36+
line. If not set, pull-down is not used.
37+
38+
rockchip,output-tapdelay-select:
39+
$ref: /schemas/types.yaml#/definitions/uint32
40+
description:
41+
Specifies the phyctrl_otapdlysec register.
42+
default: 0x4
43+
maximum: 0xf
44+
45+
"#phy-cells":
46+
const: 0
47+
48+
required:
49+
- compatible
50+
- reg
51+
- "#phy-cells"
52+
53+
additionalProperties: false
54+
55+
examples:
56+
- |
57+
phy@f780 {
58+
compatible = "rockchip,rk3399-emmc-phy";
59+
reg = <0xf780 0x20>;
60+
clocks = <&sdhci>;
61+
clock-names = "emmcclk";
62+
drive-impedance-ohm = <50>;
63+
#phy-cells = <0>;
64+
};

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