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Sam Protsenkokrzk
Sam Protsenko
authored and
krzk
committed
clk: samsung: exynos850: Implement CMU_IS domain
CMU_IS clock domain provides clocks for IS IP-core (Image Signal Processing Subsystem). According to Exynos850 TRM, CMU_IS generates CSIS, IPP, ITP, VRA and GDC clocks for BLK_IS. This patch adds next clocks: - bus clocks in CMU_TOP needed for CMU_IS - all internal CMU_IS clocks - leaf clocks for IS IP-core, CSIS (Camera Serial Interface Slave), D_TZPC (TrustZone Protection Controller), CSIS DMA, GDC (Geometric Distortion Correction), IPP (Image Preprocessing Processing core), ITP (Image Texture Processing core), MCSC (Multi-Channel Scaler), VRA (Visual Recognition Accelerator), PPMU (Platform Performance Monitoring Unit), SysMMU and SysReg IS related gate clocks in CMU_TOP were marked as CLK_IS_CRITICAL, because: 1. All of those have to be enabled in order to read /sys/kernel/debug/clk/clk_summary file 2. When some user driver (e.g. exynos-sysmmu) disables some derived leaf clock, it can lead to CMU_TOP clocks disable, which then makes the system hang. To prevent that, the CLK_IS_CRITICAL flag is used, as CLK_IGNORE_UNUSED is not enough. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220809113323.29965-7-semen.protsenko@linaro.org
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‎drivers/clk/samsung/clk-exynos850.c

Lines changed: 199 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,10 @@
3939
#define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c
4040
#define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040
4141
#define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044
42+
#define CLK_CON_MUX_MUX_CLKCMU_IS_BUS 0x1048
43+
#define CLK_CON_MUX_MUX_CLKCMU_IS_GDC 0x104c
44+
#define CLK_CON_MUX_MUX_CLKCMU_IS_ITP 0x1050
45+
#define CLK_CON_MUX_MUX_CLKCMU_IS_VRA 0x1054
4246
#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070
4347
#define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
4448
#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
@@ -52,6 +56,10 @@
5256
#define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848
5357
#define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c
5458
#define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850
59+
#define CLK_CON_DIV_CLKCMU_IS_BUS 0x1854
60+
#define CLK_CON_DIV_CLKCMU_IS_GDC 0x1858
61+
#define CLK_CON_DIV_CLKCMU_IS_ITP 0x185c
62+
#define CLK_CON_DIV_CLKCMU_IS_VRA 0x1860
5563
#define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c
5664
#define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880
5765
#define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884
@@ -71,6 +79,10 @@
7179
#define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044
7280
#define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048
7381
#define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c
82+
#define CLK_CON_GAT_GATE_CLKCMU_IS_BUS 0x2050
83+
#define CLK_CON_GAT_GATE_CLKCMU_IS_GDC 0x2054
84+
#define CLK_CON_GAT_GATE_CLKCMU_IS_ITP 0x2058
85+
#define CLK_CON_GAT_GATE_CLKCMU_IS_VRA 0x205c
7486
#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080
7587
#define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084
7688
#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088
@@ -95,6 +107,10 @@ static const unsigned long top_clk_regs[] __initconst = {
95107
CLK_CON_MUX_MUX_CLKCMU_HSI_BUS,
96108
CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD,
97109
CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD,
110+
CLK_CON_MUX_MUX_CLKCMU_IS_BUS,
111+
CLK_CON_MUX_MUX_CLKCMU_IS_GDC,
112+
CLK_CON_MUX_MUX_CLKCMU_IS_ITP,
113+
CLK_CON_MUX_MUX_CLKCMU_IS_VRA,
98114
CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
99115
CLK_CON_MUX_MUX_CLKCMU_PERI_IP,
100116
CLK_CON_MUX_MUX_CLKCMU_PERI_UART,
@@ -108,6 +124,10 @@ static const unsigned long top_clk_regs[] __initconst = {
108124
CLK_CON_DIV_CLKCMU_HSI_BUS,
109125
CLK_CON_DIV_CLKCMU_HSI_MMC_CARD,
110126
CLK_CON_DIV_CLKCMU_HSI_USB20DRD,
127+
CLK_CON_DIV_CLKCMU_IS_BUS,
128+
CLK_CON_DIV_CLKCMU_IS_GDC,
129+
CLK_CON_DIV_CLKCMU_IS_ITP,
130+
CLK_CON_DIV_CLKCMU_IS_VRA,
111131
CLK_CON_DIV_CLKCMU_PERI_BUS,
112132
CLK_CON_DIV_CLKCMU_PERI_IP,
113133
CLK_CON_DIV_CLKCMU_PERI_UART,
@@ -127,6 +147,10 @@ static const unsigned long top_clk_regs[] __initconst = {
127147
CLK_CON_GAT_GATE_CLKCMU_HSI_BUS,
128148
CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD,
129149
CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD,
150+
CLK_CON_GAT_GATE_CLKCMU_IS_BUS,
151+
CLK_CON_GAT_GATE_CLKCMU_IS_GDC,
152+
CLK_CON_GAT_GATE_CLKCMU_IS_ITP,
153+
CLK_CON_GAT_GATE_CLKCMU_IS_VRA,
130154
CLK_CON_GAT_GATE_CLKCMU_PERI_BUS,
131155
CLK_CON_GAT_GATE_CLKCMU_PERI_IP,
132156
CLK_CON_GAT_GATE_CLKCMU_PERI_UART,
@@ -176,6 +200,15 @@ PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2",
176200
"oscclk", "oscclk" };
177201
PNAME(mout_hsi_usb20drd_p) = { "oscclk", "dout_shared0_div4",
178202
"dout_shared1_div4", "oscclk" };
203+
/* List of parent clocks for Muxes in CMU_TOP: for CMU_IS */
204+
PNAME(mout_is_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
205+
"dout_shared0_div3", "dout_shared1_div3" };
206+
PNAME(mout_is_itp_p) = { "dout_shared0_div2", "dout_shared1_div2",
207+
"dout_shared0_div3", "dout_shared1_div3" };
208+
PNAME(mout_is_vra_p) = { "dout_shared0_div2", "dout_shared1_div2",
209+
"dout_shared0_div3", "dout_shared1_div3" };
210+
PNAME(mout_is_gdc_p) = { "dout_shared0_div2", "dout_shared1_div2",
211+
"dout_shared0_div3", "dout_shared1_div3" };
179212
/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
180213
PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" };
181214
PNAME(mout_peri_uart_p) = { "oscclk", "dout_shared0_div4",
@@ -225,6 +258,16 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
225258
MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p,
226259
CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2),
227260

261+
/* IS */
262+
MUX(CLK_MOUT_IS_BUS, "mout_is_bus", mout_is_bus_p,
263+
CLK_CON_MUX_MUX_CLKCMU_IS_BUS, 0, 2),
264+
MUX(CLK_MOUT_IS_ITP, "mout_is_itp", mout_is_itp_p,
265+
CLK_CON_MUX_MUX_CLKCMU_IS_ITP, 0, 2),
266+
MUX(CLK_MOUT_IS_VRA, "mout_is_vra", mout_is_vra_p,
267+
CLK_CON_MUX_MUX_CLKCMU_IS_VRA, 0, 2),
268+
MUX(CLK_MOUT_IS_GDC, "mout_is_gdc", mout_is_gdc_p,
269+
CLK_CON_MUX_MUX_CLKCMU_IS_GDC, 0, 2),
270+
228271
/* PERI */
229272
MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
230273
CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
@@ -279,6 +322,16 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
279322
DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd",
280323
CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4),
281324

325+
/* IS */
326+
DIV(CLK_DOUT_IS_BUS, "dout_is_bus", "gout_is_bus",
327+
CLK_CON_DIV_CLKCMU_IS_BUS, 0, 4),
328+
DIV(CLK_DOUT_IS_ITP, "dout_is_itp", "gout_is_itp",
329+
CLK_CON_DIV_CLKCMU_IS_ITP, 0, 4),
330+
DIV(CLK_DOUT_IS_VRA, "dout_is_vra", "gout_is_vra",
331+
CLK_CON_DIV_CLKCMU_IS_VRA, 0, 4),
332+
DIV(CLK_DOUT_IS_GDC, "dout_is_gdc", "gout_is_gdc",
333+
CLK_CON_DIV_CLKCMU_IS_GDC, 0, 4),
334+
282335
/* PERI */
283336
DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
284337
CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
@@ -319,6 +372,17 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
319372
GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd",
320373
CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0),
321374

375+
/* IS */
376+
/* TODO: These clocks have to be always enabled to access CMU_IS regs */
377+
GATE(CLK_GOUT_IS_BUS, "gout_is_bus", "mout_is_bus",
378+
CLK_CON_GAT_GATE_CLKCMU_IS_BUS, 21, CLK_IS_CRITICAL, 0),
379+
GATE(CLK_GOUT_IS_ITP, "gout_is_itp", "mout_is_itp",
380+
CLK_CON_GAT_GATE_CLKCMU_IS_ITP, 21, CLK_IS_CRITICAL, 0),
381+
GATE(CLK_GOUT_IS_VRA, "gout_is_vra", "mout_is_vra",
382+
CLK_CON_GAT_GATE_CLKCMU_IS_VRA, 21, CLK_IS_CRITICAL, 0),
383+
GATE(CLK_GOUT_IS_GDC, "gout_is_gdc", "mout_is_gdc",
384+
CLK_CON_GAT_GATE_CLKCMU_IS_GDC, 21, CLK_IS_CRITICAL, 0),
385+
322386
/* PERI */
323387
GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus",
324388
CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
@@ -952,6 +1016,138 @@ static const struct samsung_cmu_info hsi_cmu_info __initconst = {
9521016
.clk_name = "dout_hsi_bus",
9531017
};
9541018

1019+
/* ---- CMU_IS -------------------------------------------------------------- */
1020+
1021+
#define PLL_CON0_MUX_CLKCMU_IS_BUS_USER 0x0600
1022+
#define PLL_CON0_MUX_CLKCMU_IS_GDC_USER 0x0610
1023+
#define PLL_CON0_MUX_CLKCMU_IS_ITP_USER 0x0620
1024+
#define PLL_CON0_MUX_CLKCMU_IS_VRA_USER 0x0630
1025+
#define CLK_CON_DIV_DIV_CLK_IS_BUSP 0x1800
1026+
#define CLK_CON_GAT_CLK_IS_CMU_IS_PCLK 0x2000
1027+
#define CLK_CON_GAT_GOUT_IS_CSIS0_ACLK 0x2040
1028+
#define CLK_CON_GAT_GOUT_IS_CSIS1_ACLK 0x2044
1029+
#define CLK_CON_GAT_GOUT_IS_CSIS2_ACLK 0x2048
1030+
#define CLK_CON_GAT_GOUT_IS_TZPC_PCLK 0x204c
1031+
#define CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA 0x2050
1032+
#define CLK_CON_GAT_GOUT_IS_CLK_GDC 0x2054
1033+
#define CLK_CON_GAT_GOUT_IS_CLK_IPP 0x2058
1034+
#define CLK_CON_GAT_GOUT_IS_CLK_ITP 0x205c
1035+
#define CLK_CON_GAT_GOUT_IS_CLK_MCSC 0x2060
1036+
#define CLK_CON_GAT_GOUT_IS_CLK_VRA 0x2064
1037+
#define CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK 0x2074
1038+
#define CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK 0x2078
1039+
#define CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK 0x207c
1040+
#define CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK 0x2080
1041+
#define CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1 0x2098
1042+
#define CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1 0x209c
1043+
#define CLK_CON_GAT_GOUT_IS_SYSREG_PCLK 0x20a0
1044+
1045+
static const unsigned long is_clk_regs[] __initconst = {
1046+
PLL_CON0_MUX_CLKCMU_IS_BUS_USER,
1047+
PLL_CON0_MUX_CLKCMU_IS_GDC_USER,
1048+
PLL_CON0_MUX_CLKCMU_IS_ITP_USER,
1049+
PLL_CON0_MUX_CLKCMU_IS_VRA_USER,
1050+
CLK_CON_DIV_DIV_CLK_IS_BUSP,
1051+
CLK_CON_GAT_CLK_IS_CMU_IS_PCLK,
1052+
CLK_CON_GAT_GOUT_IS_CSIS0_ACLK,
1053+
CLK_CON_GAT_GOUT_IS_CSIS1_ACLK,
1054+
CLK_CON_GAT_GOUT_IS_CSIS2_ACLK,
1055+
CLK_CON_GAT_GOUT_IS_TZPC_PCLK,
1056+
CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA,
1057+
CLK_CON_GAT_GOUT_IS_CLK_GDC,
1058+
CLK_CON_GAT_GOUT_IS_CLK_IPP,
1059+
CLK_CON_GAT_GOUT_IS_CLK_ITP,
1060+
CLK_CON_GAT_GOUT_IS_CLK_MCSC,
1061+
CLK_CON_GAT_GOUT_IS_CLK_VRA,
1062+
CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK,
1063+
CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK,
1064+
CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK,
1065+
CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK,
1066+
CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1,
1067+
CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1,
1068+
CLK_CON_GAT_GOUT_IS_SYSREG_PCLK,
1069+
};
1070+
1071+
/* List of parent clocks for Muxes in CMU_IS */
1072+
PNAME(mout_is_bus_user_p) = { "oscclk", "dout_is_bus" };
1073+
PNAME(mout_is_itp_user_p) = { "oscclk", "dout_is_itp" };
1074+
PNAME(mout_is_vra_user_p) = { "oscclk", "dout_is_vra" };
1075+
PNAME(mout_is_gdc_user_p) = { "oscclk", "dout_is_gdc" };
1076+
1077+
static const struct samsung_mux_clock is_mux_clks[] __initconst = {
1078+
MUX(CLK_MOUT_IS_BUS_USER, "mout_is_bus_user", mout_is_bus_user_p,
1079+
PLL_CON0_MUX_CLKCMU_IS_BUS_USER, 4, 1),
1080+
MUX(CLK_MOUT_IS_ITP_USER, "mout_is_itp_user", mout_is_itp_user_p,
1081+
PLL_CON0_MUX_CLKCMU_IS_ITP_USER, 4, 1),
1082+
MUX(CLK_MOUT_IS_VRA_USER, "mout_is_vra_user", mout_is_vra_user_p,
1083+
PLL_CON0_MUX_CLKCMU_IS_VRA_USER, 4, 1),
1084+
MUX(CLK_MOUT_IS_GDC_USER, "mout_is_gdc_user", mout_is_gdc_user_p,
1085+
PLL_CON0_MUX_CLKCMU_IS_GDC_USER, 4, 1),
1086+
};
1087+
1088+
static const struct samsung_div_clock is_div_clks[] __initconst = {
1089+
DIV(CLK_DOUT_IS_BUSP, "dout_is_busp", "mout_is_bus_user",
1090+
CLK_CON_DIV_DIV_CLK_IS_BUSP, 0, 2),
1091+
};
1092+
1093+
static const struct samsung_gate_clock is_gate_clks[] __initconst = {
1094+
/* TODO: Should be enabled in IS driver */
1095+
GATE(CLK_GOUT_IS_CMU_IS_PCLK, "gout_is_cmu_is_pclk", "dout_is_busp",
1096+
CLK_CON_GAT_CLK_IS_CMU_IS_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1097+
GATE(CLK_GOUT_IS_CSIS0_ACLK, "gout_is_csis0_aclk", "mout_is_bus_user",
1098+
CLK_CON_GAT_GOUT_IS_CSIS0_ACLK, 21, 0, 0),
1099+
GATE(CLK_GOUT_IS_CSIS1_ACLK, "gout_is_csis1_aclk", "mout_is_bus_user",
1100+
CLK_CON_GAT_GOUT_IS_CSIS1_ACLK, 21, 0, 0),
1101+
GATE(CLK_GOUT_IS_CSIS2_ACLK, "gout_is_csis2_aclk", "mout_is_bus_user",
1102+
CLK_CON_GAT_GOUT_IS_CSIS2_ACLK, 21, 0, 0),
1103+
GATE(CLK_GOUT_IS_TZPC_PCLK, "gout_is_tzpc_pclk", "dout_is_busp",
1104+
CLK_CON_GAT_GOUT_IS_TZPC_PCLK, 21, 0, 0),
1105+
GATE(CLK_GOUT_IS_CSIS_DMA_CLK, "gout_is_csis_dma_clk",
1106+
"mout_is_bus_user",
1107+
CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA, 21, 0, 0),
1108+
GATE(CLK_GOUT_IS_GDC_CLK, "gout_is_gdc_clk", "mout_is_gdc_user",
1109+
CLK_CON_GAT_GOUT_IS_CLK_GDC, 21, 0, 0),
1110+
GATE(CLK_GOUT_IS_IPP_CLK, "gout_is_ipp_clk", "mout_is_bus_user",
1111+
CLK_CON_GAT_GOUT_IS_CLK_IPP, 21, 0, 0),
1112+
GATE(CLK_GOUT_IS_ITP_CLK, "gout_is_itp_clk", "mout_is_itp_user",
1113+
CLK_CON_GAT_GOUT_IS_CLK_ITP, 21, 0, 0),
1114+
GATE(CLK_GOUT_IS_MCSC_CLK, "gout_is_mcsc_clk", "mout_is_itp_user",
1115+
CLK_CON_GAT_GOUT_IS_CLK_MCSC, 21, 0, 0),
1116+
GATE(CLK_GOUT_IS_VRA_CLK, "gout_is_vra_clk", "mout_is_vra_user",
1117+
CLK_CON_GAT_GOUT_IS_CLK_VRA, 21, 0, 0),
1118+
GATE(CLK_GOUT_IS_PPMU_IS0_ACLK, "gout_is_ppmu_is0_aclk",
1119+
"mout_is_bus_user",
1120+
CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK, 21, 0, 0),
1121+
GATE(CLK_GOUT_IS_PPMU_IS0_PCLK, "gout_is_ppmu_is0_pclk", "dout_is_busp",
1122+
CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK, 21, 0, 0),
1123+
GATE(CLK_GOUT_IS_PPMU_IS1_ACLK, "gout_is_ppmu_is1_aclk",
1124+
"mout_is_itp_user",
1125+
CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK, 21, 0, 0),
1126+
GATE(CLK_GOUT_IS_PPMU_IS1_PCLK, "gout_is_ppmu_is1_pclk", "dout_is_busp",
1127+
CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK, 21, 0, 0),
1128+
GATE(CLK_GOUT_IS_SYSMMU_IS0_CLK, "gout_is_sysmmu_is0_clk",
1129+
"mout_is_bus_user",
1130+
CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1, 21, 0, 0),
1131+
GATE(CLK_GOUT_IS_SYSMMU_IS1_CLK, "gout_is_sysmmu_is1_clk",
1132+
"mout_is_itp_user",
1133+
CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1, 21, 0, 0),
1134+
GATE(CLK_GOUT_IS_SYSREG_PCLK, "gout_is_sysreg_pclk", "dout_is_busp",
1135+
CLK_CON_GAT_GOUT_IS_SYSREG_PCLK, 21, 0, 0),
1136+
};
1137+
1138+
static const struct samsung_cmu_info is_cmu_info __initconst = {
1139+
.mux_clks = is_mux_clks,
1140+
.nr_mux_clks = ARRAY_SIZE(is_mux_clks),
1141+
.div_clks = is_div_clks,
1142+
.nr_div_clks = ARRAY_SIZE(is_div_clks),
1143+
.gate_clks = is_gate_clks,
1144+
.nr_gate_clks = ARRAY_SIZE(is_gate_clks),
1145+
.nr_clk_ids = IS_NR_CLK,
1146+
.clk_regs = is_clk_regs,
1147+
.nr_clk_regs = ARRAY_SIZE(is_clk_regs),
1148+
.clk_name = "dout_is_bus",
1149+
};
1150+
9551151
/* ---- CMU_PERI ------------------------------------------------------------ */
9561152

9571153
/* Register Offset definitions for CMU_PERI (0x10030000) */
@@ -1334,6 +1530,9 @@ static const struct of_device_id exynos850_cmu_of_match[] = {
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}, {
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.compatible = "samsung,exynos850-cmu-hsi",
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.data = &hsi_cmu_info,
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}, {
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.compatible = "samsung,exynos850-cmu-is",
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.data = &is_cmu_info,
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}, {
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.compatible = "samsung,exynos850-cmu-core",
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.data = &core_cmu_info,

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