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Kartik RajputJassi Brar
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mailbox: tegra-hsp: Define dimensioning masks in SoC data
Tegra264 has updated HSP_INT_DIMENSIONING register as follows: * nSI is now BIT17:BIT21. * nDB is now BIT12:BIT16. Currently, we are using a static macro HSP_nINT_MASK to get the values from HSP_INT_DIMENSIONING register. This results in wrong values for nSI for HSP instances that supports 16 shared interrupts. Define dimensioning masks in soc data and use them to parse nSI, nDB, nAS, nSS & nSM values. Fixes: 602dbba ("mailbox: tegra: add support for Tegra264") Cc: stable@vger.kernel.org Signed-off-by: Kartik Rajput <kkartik@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
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drivers/mailbox/tegra-hsp.c

Lines changed: 60 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// SPDX-License-Identifier: GPL-2.0-only
22
/*
3-
* Copyright (c) 2016-2023, NVIDIA CORPORATION. All rights reserved.
3+
* Copyright (c) 2016-2025, NVIDIA CORPORATION. All rights reserved.
44
*/
55

66
#include <linux/delay.h>
@@ -28,12 +28,6 @@
2828
#define HSP_INT_FULL_MASK 0xff
2929

3030
#define HSP_INT_DIMENSIONING 0x380
31-
#define HSP_nSM_SHIFT 0
32-
#define HSP_nSS_SHIFT 4
33-
#define HSP_nAS_SHIFT 8
34-
#define HSP_nDB_SHIFT 12
35-
#define HSP_nSI_SHIFT 16
36-
#define HSP_nINT_MASK 0xf
3731

3832
#define HSP_DB_TRIGGER 0x0
3933
#define HSP_DB_ENABLE 0x4
@@ -97,6 +91,20 @@ struct tegra_hsp_soc {
9791
bool has_per_mb_ie;
9892
bool has_128_bit_mb;
9993
unsigned int reg_stride;
94+
95+
/* Shifts for dimensioning register. */
96+
unsigned int si_shift;
97+
unsigned int db_shift;
98+
unsigned int as_shift;
99+
unsigned int ss_shift;
100+
unsigned int sm_shift;
101+
102+
/* Masks for dimensioning register. */
103+
unsigned int si_mask;
104+
unsigned int db_mask;
105+
unsigned int as_mask;
106+
unsigned int ss_mask;
107+
unsigned int sm_mask;
100108
};
101109

102110
struct tegra_hsp {
@@ -747,11 +755,11 @@ static int tegra_hsp_probe(struct platform_device *pdev)
747755
return PTR_ERR(hsp->regs);
748756

749757
value = tegra_hsp_readl(hsp, HSP_INT_DIMENSIONING);
750-
hsp->num_sm = (value >> HSP_nSM_SHIFT) & HSP_nINT_MASK;
751-
hsp->num_ss = (value >> HSP_nSS_SHIFT) & HSP_nINT_MASK;
752-
hsp->num_as = (value >> HSP_nAS_SHIFT) & HSP_nINT_MASK;
753-
hsp->num_db = (value >> HSP_nDB_SHIFT) & HSP_nINT_MASK;
754-
hsp->num_si = (value >> HSP_nSI_SHIFT) & HSP_nINT_MASK;
758+
hsp->num_sm = (value >> hsp->soc->sm_shift) & hsp->soc->sm_mask;
759+
hsp->num_ss = (value >> hsp->soc->ss_shift) & hsp->soc->ss_mask;
760+
hsp->num_as = (value >> hsp->soc->as_shift) & hsp->soc->as_mask;
761+
hsp->num_db = (value >> hsp->soc->db_shift) & hsp->soc->db_mask;
762+
hsp->num_si = (value >> hsp->soc->si_shift) & hsp->soc->si_mask;
755763

756764
err = platform_get_irq_byname_optional(pdev, "doorbell");
757765
if (err >= 0)
@@ -915,27 +923,67 @@ static const struct tegra_hsp_soc tegra186_hsp_soc = {
915923
.has_per_mb_ie = false,
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.has_128_bit_mb = false,
917925
.reg_stride = 0x100,
926+
.si_shift = 16,
927+
.db_shift = 12,
928+
.as_shift = 8,
929+
.ss_shift = 4,
930+
.sm_shift = 0,
931+
.si_mask = 0xf,
932+
.db_mask = 0xf,
933+
.as_mask = 0xf,
934+
.ss_mask = 0xf,
935+
.sm_mask = 0xf,
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};
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920938
static const struct tegra_hsp_soc tegra194_hsp_soc = {
921939
.map = tegra186_hsp_db_map,
922940
.has_per_mb_ie = true,
923941
.has_128_bit_mb = false,
924942
.reg_stride = 0x100,
943+
.si_shift = 16,
944+
.db_shift = 12,
945+
.as_shift = 8,
946+
.ss_shift = 4,
947+
.sm_shift = 0,
948+
.si_mask = 0xf,
949+
.db_mask = 0xf,
950+
.as_mask = 0xf,
951+
.ss_mask = 0xf,
952+
.sm_mask = 0xf,
925953
};
926954

927955
static const struct tegra_hsp_soc tegra234_hsp_soc = {
928956
.map = tegra186_hsp_db_map,
929957
.has_per_mb_ie = false,
930958
.has_128_bit_mb = true,
931959
.reg_stride = 0x100,
960+
.si_shift = 16,
961+
.db_shift = 12,
962+
.as_shift = 8,
963+
.ss_shift = 4,
964+
.sm_shift = 0,
965+
.si_mask = 0xf,
966+
.db_mask = 0xf,
967+
.as_mask = 0xf,
968+
.ss_mask = 0xf,
969+
.sm_mask = 0xf,
932970
};
933971

934972
static const struct tegra_hsp_soc tegra264_hsp_soc = {
935973
.map = tegra186_hsp_db_map,
936974
.has_per_mb_ie = false,
937975
.has_128_bit_mb = true,
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.reg_stride = 0x1000,
977+
.si_shift = 17,
978+
.db_shift = 12,
979+
.as_shift = 8,
980+
.ss_shift = 4,
981+
.sm_shift = 0,
982+
.si_mask = 0x1f,
983+
.db_mask = 0x1f,
984+
.as_mask = 0xf,
985+
.ss_mask = 0xf,
986+
.sm_mask = 0xf,
939987
};
940988

941989
static const struct of_device_id tegra_hsp_match[] = {

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