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1 | 1 | // SPDX-License-Identifier: GPL-2.0-only
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2 | 2 | /*
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3 |
| - * Copyright (c) 2016-2023, NVIDIA CORPORATION. All rights reserved. |
| 3 | + * Copyright (c) 2016-2025, NVIDIA CORPORATION. All rights reserved. |
4 | 4 | */
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5 | 5 |
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6 | 6 | #include <linux/delay.h>
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28 | 28 | #define HSP_INT_FULL_MASK 0xff
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29 | 29 |
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30 | 30 | #define HSP_INT_DIMENSIONING 0x380
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31 |
| -#define HSP_nSM_SHIFT 0 |
32 |
| -#define HSP_nSS_SHIFT 4 |
33 |
| -#define HSP_nAS_SHIFT 8 |
34 |
| -#define HSP_nDB_SHIFT 12 |
35 |
| -#define HSP_nSI_SHIFT 16 |
36 |
| -#define HSP_nINT_MASK 0xf |
37 | 31 |
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38 | 32 | #define HSP_DB_TRIGGER 0x0
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39 | 33 | #define HSP_DB_ENABLE 0x4
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@@ -97,6 +91,20 @@ struct tegra_hsp_soc {
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97 | 91 | bool has_per_mb_ie;
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98 | 92 | bool has_128_bit_mb;
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99 | 93 | unsigned int reg_stride;
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| 94 | + |
| 95 | + /* Shifts for dimensioning register. */ |
| 96 | + unsigned int si_shift; |
| 97 | + unsigned int db_shift; |
| 98 | + unsigned int as_shift; |
| 99 | + unsigned int ss_shift; |
| 100 | + unsigned int sm_shift; |
| 101 | + |
| 102 | + /* Masks for dimensioning register. */ |
| 103 | + unsigned int si_mask; |
| 104 | + unsigned int db_mask; |
| 105 | + unsigned int as_mask; |
| 106 | + unsigned int ss_mask; |
| 107 | + unsigned int sm_mask; |
100 | 108 | };
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101 | 109 |
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102 | 110 | struct tegra_hsp {
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@@ -747,11 +755,11 @@ static int tegra_hsp_probe(struct platform_device *pdev)
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747 | 755 | return PTR_ERR(hsp->regs);
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748 | 756 |
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749 | 757 | value = tegra_hsp_readl(hsp, HSP_INT_DIMENSIONING);
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750 |
| - hsp->num_sm = (value >> HSP_nSM_SHIFT) & HSP_nINT_MASK; |
751 |
| - hsp->num_ss = (value >> HSP_nSS_SHIFT) & HSP_nINT_MASK; |
752 |
| - hsp->num_as = (value >> HSP_nAS_SHIFT) & HSP_nINT_MASK; |
753 |
| - hsp->num_db = (value >> HSP_nDB_SHIFT) & HSP_nINT_MASK; |
754 |
| - hsp->num_si = (value >> HSP_nSI_SHIFT) & HSP_nINT_MASK; |
| 758 | + hsp->num_sm = (value >> hsp->soc->sm_shift) & hsp->soc->sm_mask; |
| 759 | + hsp->num_ss = (value >> hsp->soc->ss_shift) & hsp->soc->ss_mask; |
| 760 | + hsp->num_as = (value >> hsp->soc->as_shift) & hsp->soc->as_mask; |
| 761 | + hsp->num_db = (value >> hsp->soc->db_shift) & hsp->soc->db_mask; |
| 762 | + hsp->num_si = (value >> hsp->soc->si_shift) & hsp->soc->si_mask; |
755 | 763 |
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756 | 764 | err = platform_get_irq_byname_optional(pdev, "doorbell");
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757 | 765 | if (err >= 0)
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@@ -915,27 +923,67 @@ static const struct tegra_hsp_soc tegra186_hsp_soc = {
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915 | 923 | .has_per_mb_ie = false,
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916 | 924 | .has_128_bit_mb = false,
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917 | 925 | .reg_stride = 0x100,
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| 926 | + .si_shift = 16, |
| 927 | + .db_shift = 12, |
| 928 | + .as_shift = 8, |
| 929 | + .ss_shift = 4, |
| 930 | + .sm_shift = 0, |
| 931 | + .si_mask = 0xf, |
| 932 | + .db_mask = 0xf, |
| 933 | + .as_mask = 0xf, |
| 934 | + .ss_mask = 0xf, |
| 935 | + .sm_mask = 0xf, |
918 | 936 | };
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919 | 937 |
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920 | 938 | static const struct tegra_hsp_soc tegra194_hsp_soc = {
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921 | 939 | .map = tegra186_hsp_db_map,
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922 | 940 | .has_per_mb_ie = true,
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923 | 941 | .has_128_bit_mb = false,
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924 | 942 | .reg_stride = 0x100,
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| 943 | + .si_shift = 16, |
| 944 | + .db_shift = 12, |
| 945 | + .as_shift = 8, |
| 946 | + .ss_shift = 4, |
| 947 | + .sm_shift = 0, |
| 948 | + .si_mask = 0xf, |
| 949 | + .db_mask = 0xf, |
| 950 | + .as_mask = 0xf, |
| 951 | + .ss_mask = 0xf, |
| 952 | + .sm_mask = 0xf, |
925 | 953 | };
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926 | 954 |
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927 | 955 | static const struct tegra_hsp_soc tegra234_hsp_soc = {
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928 | 956 | .map = tegra186_hsp_db_map,
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929 | 957 | .has_per_mb_ie = false,
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930 | 958 | .has_128_bit_mb = true,
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931 | 959 | .reg_stride = 0x100,
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| 960 | + .si_shift = 16, |
| 961 | + .db_shift = 12, |
| 962 | + .as_shift = 8, |
| 963 | + .ss_shift = 4, |
| 964 | + .sm_shift = 0, |
| 965 | + .si_mask = 0xf, |
| 966 | + .db_mask = 0xf, |
| 967 | + .as_mask = 0xf, |
| 968 | + .ss_mask = 0xf, |
| 969 | + .sm_mask = 0xf, |
932 | 970 | };
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933 | 971 |
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934 | 972 | static const struct tegra_hsp_soc tegra264_hsp_soc = {
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935 | 973 | .map = tegra186_hsp_db_map,
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936 | 974 | .has_per_mb_ie = false,
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937 | 975 | .has_128_bit_mb = true,
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938 | 976 | .reg_stride = 0x1000,
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| 977 | + .si_shift = 17, |
| 978 | + .db_shift = 12, |
| 979 | + .as_shift = 8, |
| 980 | + .ss_shift = 4, |
| 981 | + .sm_shift = 0, |
| 982 | + .si_mask = 0x1f, |
| 983 | + .db_mask = 0x1f, |
| 984 | + .as_mask = 0xf, |
| 985 | + .ss_mask = 0xf, |
| 986 | + .sm_mask = 0xf, |
939 | 987 | };
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940 | 988 |
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941 | 989 | static const struct of_device_id tegra_hsp_match[] = {
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