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arndbbebarino
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clk: tegra20: fix gcc-7 constant overflow warning
Older gcc versions get confused by comparing a u32 value to a negative constant in a switch()/case block: drivers/clk/tegra/clk-tegra20.c: In function 'tegra20_clk_measure_input_freq': drivers/clk/tegra/clk-tegra20.c:581:2: error: case label does not reduce to an integer constant case OSC_CTRL_OSC_FREQ_12MHZ: ^~~~ drivers/clk/tegra/clk-tegra20.c:593:2: error: case label does not reduce to an integer constant case OSC_CTRL_OSC_FREQ_26MHZ: Make the constants unsigned instead. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20230227085914.2560984-1-arnd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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drivers/clk/tegra/clk-tegra20.c

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -21,24 +21,24 @@
2121
#define MISC_CLK_ENB 0x48
2222

2323
#define OSC_CTRL 0x50
24-
#define OSC_CTRL_OSC_FREQ_MASK (3<<30)
25-
#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
26-
#define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
27-
#define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
28-
#define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
29-
#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
30-
31-
#define OSC_CTRL_PLL_REF_DIV_MASK (3<<28)
32-
#define OSC_CTRL_PLL_REF_DIV_1 (0<<28)
33-
#define OSC_CTRL_PLL_REF_DIV_2 (1<<28)
34-
#define OSC_CTRL_PLL_REF_DIV_4 (2<<28)
24+
#define OSC_CTRL_OSC_FREQ_MASK (3u<<30)
25+
#define OSC_CTRL_OSC_FREQ_13MHZ (0u<<30)
26+
#define OSC_CTRL_OSC_FREQ_19_2MHZ (1u<<30)
27+
#define OSC_CTRL_OSC_FREQ_12MHZ (2u<<30)
28+
#define OSC_CTRL_OSC_FREQ_26MHZ (3u<<30)
29+
#define OSC_CTRL_MASK (0x3f2u | OSC_CTRL_OSC_FREQ_MASK)
30+
31+
#define OSC_CTRL_PLL_REF_DIV_MASK (3u<<28)
32+
#define OSC_CTRL_PLL_REF_DIV_1 (0u<<28)
33+
#define OSC_CTRL_PLL_REF_DIV_2 (1u<<28)
34+
#define OSC_CTRL_PLL_REF_DIV_4 (2u<<28)
3535

3636
#define OSC_FREQ_DET 0x58
37-
#define OSC_FREQ_DET_TRIG (1<<31)
37+
#define OSC_FREQ_DET_TRIG (1u<<31)
3838

3939
#define OSC_FREQ_DET_STATUS 0x5c
40-
#define OSC_FREQ_DET_BUSY (1<<31)
41-
#define OSC_FREQ_DET_CNT_MASK 0xFFFF
40+
#define OSC_FREQ_DET_BUSYu (1<<31)
41+
#define OSC_FREQ_DET_CNT_MASK 0xFFFFu
4242

4343
#define TEGRA20_CLK_PERIPH_BANKS 3
4444

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