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21 | 21 | #define MISC_CLK_ENB 0x48
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22 | 22 |
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23 | 23 | #define OSC_CTRL 0x50
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24 |
| -#define OSC_CTRL_OSC_FREQ_MASK (3<<30) |
25 |
| -#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30) |
26 |
| -#define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30) |
27 |
| -#define OSC_CTRL_OSC_FREQ_12MHZ (2<<30) |
28 |
| -#define OSC_CTRL_OSC_FREQ_26MHZ (3<<30) |
29 |
| -#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) |
30 |
| - |
31 |
| -#define OSC_CTRL_PLL_REF_DIV_MASK (3<<28) |
32 |
| -#define OSC_CTRL_PLL_REF_DIV_1 (0<<28) |
33 |
| -#define OSC_CTRL_PLL_REF_DIV_2 (1<<28) |
34 |
| -#define OSC_CTRL_PLL_REF_DIV_4 (2<<28) |
| 24 | +#define OSC_CTRL_OSC_FREQ_MASK (3u<<30) |
| 25 | +#define OSC_CTRL_OSC_FREQ_13MHZ (0u<<30) |
| 26 | +#define OSC_CTRL_OSC_FREQ_19_2MHZ (1u<<30) |
| 27 | +#define OSC_CTRL_OSC_FREQ_12MHZ (2u<<30) |
| 28 | +#define OSC_CTRL_OSC_FREQ_26MHZ (3u<<30) |
| 29 | +#define OSC_CTRL_MASK (0x3f2u | OSC_CTRL_OSC_FREQ_MASK) |
| 30 | + |
| 31 | +#define OSC_CTRL_PLL_REF_DIV_MASK (3u<<28) |
| 32 | +#define OSC_CTRL_PLL_REF_DIV_1 (0u<<28) |
| 33 | +#define OSC_CTRL_PLL_REF_DIV_2 (1u<<28) |
| 34 | +#define OSC_CTRL_PLL_REF_DIV_4 (2u<<28) |
35 | 35 |
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36 | 36 | #define OSC_FREQ_DET 0x58
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37 |
| -#define OSC_FREQ_DET_TRIG (1<<31) |
| 37 | +#define OSC_FREQ_DET_TRIG (1u<<31) |
38 | 38 |
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39 | 39 | #define OSC_FREQ_DET_STATUS 0x5c
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40 |
| -#define OSC_FREQ_DET_BUSY (1<<31) |
41 |
| -#define OSC_FREQ_DET_CNT_MASK 0xFFFF |
| 40 | +#define OSC_FREQ_DET_BUSYu (1<<31) |
| 41 | +#define OSC_FREQ_DET_CNT_MASK 0xFFFFu |
42 | 42 |
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43 | 43 | #define TEGRA20_CLK_PERIPH_BANKS 3
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44 | 44 |
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