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airliedairlied
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Merge tag 'drm-intel-fixes-2024-05-08' of https://anongit.freedesktop.org/git/drm/drm-intel into drm-fixes
- Automate CCS Mode setting during engine resets (Andi) - Fix audio time stamp programming for DP (Chaitanya) - Fix parsing backlight BDB data (Karthikeyan) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ZjvTVEmQeVKVB2jx@intel.com
2 parents dd5a440 + 43b26bd commit b356ead

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6 files changed

+19
-130
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6 files changed

+19
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lines changed

‎drivers/gpu/drm/i915/display/intel_audio.c

Lines changed: 8 additions & 105 deletions
Original file line numberDiff line numberDiff line change
@@ -76,80 +76,13 @@ struct intel_audio_funcs {
7676
struct intel_crtc_state *crtc_state);
7777
};
7878

79-
/* DP N/M table */
80-
#define LC_810M 810000
81-
#define LC_540M 540000
82-
#define LC_270M 270000
83-
#define LC_162M 162000
84-
85-
struct dp_aud_n_m {
86-
int sample_rate;
87-
int clock;
88-
u16 m;
89-
u16 n;
90-
};
91-
9279
struct hdmi_aud_ncts {
9380
int sample_rate;
9481
int clock;
9582
int n;
9683
int cts;
9784
};
9885

99-
/* Values according to DP 1.4 Table 2-104 */
100-
static const struct dp_aud_n_m dp_aud_n_m[] = {
101-
{ 32000, LC_162M, 1024, 10125 },
102-
{ 44100, LC_162M, 784, 5625 },
103-
{ 48000, LC_162M, 512, 3375 },
104-
{ 64000, LC_162M, 2048, 10125 },
105-
{ 88200, LC_162M, 1568, 5625 },
106-
{ 96000, LC_162M, 1024, 3375 },
107-
{ 128000, LC_162M, 4096, 10125 },
108-
{ 176400, LC_162M, 3136, 5625 },
109-
{ 192000, LC_162M, 2048, 3375 },
110-
{ 32000, LC_270M, 1024, 16875 },
111-
{ 44100, LC_270M, 784, 9375 },
112-
{ 48000, LC_270M, 512, 5625 },
113-
{ 64000, LC_270M, 2048, 16875 },
114-
{ 88200, LC_270M, 1568, 9375 },
115-
{ 96000, LC_270M, 1024, 5625 },
116-
{ 128000, LC_270M, 4096, 16875 },
117-
{ 176400, LC_270M, 3136, 9375 },
118-
{ 192000, LC_270M, 2048, 5625 },
119-
{ 32000, LC_540M, 1024, 33750 },
120-
{ 44100, LC_540M, 784, 18750 },
121-
{ 48000, LC_540M, 512, 11250 },
122-
{ 64000, LC_540M, 2048, 33750 },
123-
{ 88200, LC_540M, 1568, 18750 },
124-
{ 96000, LC_540M, 1024, 11250 },
125-
{ 128000, LC_540M, 4096, 33750 },
126-
{ 176400, LC_540M, 3136, 18750 },
127-
{ 192000, LC_540M, 2048, 11250 },
128-
{ 32000, LC_810M, 1024, 50625 },
129-
{ 44100, LC_810M, 784, 28125 },
130-
{ 48000, LC_810M, 512, 16875 },
131-
{ 64000, LC_810M, 2048, 50625 },
132-
{ 88200, LC_810M, 1568, 28125 },
133-
{ 96000, LC_810M, 1024, 16875 },
134-
{ 128000, LC_810M, 4096, 50625 },
135-
{ 176400, LC_810M, 3136, 28125 },
136-
{ 192000, LC_810M, 2048, 16875 },
137-
};
138-
139-
static const struct dp_aud_n_m *
140-
audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate)
141-
{
142-
int i;
143-
144-
for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {
145-
if (rate == dp_aud_n_m[i].sample_rate &&
146-
crtc_state->port_clock == dp_aud_n_m[i].clock)
147-
return &dp_aud_n_m[i];
148-
}
149-
150-
return NULL;
151-
}
152-
15386
static const struct {
15487
int clock;
15588
u32 config;
@@ -387,47 +320,17 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
387320
const struct intel_crtc_state *crtc_state)
388321
{
389322
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
390-
struct i915_audio_component *acomp = i915->display.audio.component;
391323
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
392-
enum port port = encoder->port;
393-
const struct dp_aud_n_m *nm;
394-
int rate;
395-
u32 tmp;
396-
397-
rate = acomp ? acomp->aud_sample_rate[port] : 0;
398-
nm = audio_config_dp_get_n_m(crtc_state, rate);
399-
if (nm)
400-
drm_dbg_kms(&i915->drm, "using Maud %u, Naud %u\n", nm->m,
401-
nm->n);
402-
else
403-
drm_dbg_kms(&i915->drm, "using automatic Maud, Naud\n");
404-
405-
tmp = intel_de_read(i915, HSW_AUD_CFG(cpu_transcoder));
406-
tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
407-
tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
408-
tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
409-
tmp |= AUD_CONFIG_N_VALUE_INDEX;
410324

411-
if (nm) {
412-
tmp &= ~AUD_CONFIG_N_MASK;
413-
tmp |= AUD_CONFIG_N(nm->n);
414-
tmp |= AUD_CONFIG_N_PROG_ENABLE;
415-
}
416-
417-
intel_de_write(i915, HSW_AUD_CFG(cpu_transcoder), tmp);
418-
419-
tmp = intel_de_read(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
420-
tmp &= ~AUD_CONFIG_M_MASK;
421-
tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
422-
tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
423-
424-
if (nm) {
425-
tmp |= nm->m;
426-
tmp |= AUD_M_CTS_M_VALUE_INDEX;
427-
tmp |= AUD_M_CTS_M_PROG_ENABLE;
428-
}
325+
/* Enable time stamps. Let HW calculate Maud/Naud values */
326+
intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder),
327+
AUD_CONFIG_N_VALUE_INDEX |
328+
AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK |
329+
AUD_CONFIG_UPPER_N_MASK |
330+
AUD_CONFIG_LOWER_N_MASK |
331+
AUD_CONFIG_N_PROG_ENABLE,
332+
AUD_CONFIG_N_VALUE_INDEX);
429333

430-
intel_de_write(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
431334
}
432335

433336
static void

‎drivers/gpu/drm/i915/display/intel_bios.c

Lines changed: 4 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1042,22 +1042,11 @@ parse_lfp_backlight(struct drm_i915_private *i915,
10421042
panel->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;
10431043
panel->vbt.backlight.controller = 0;
10441044
if (i915->display.vbt.version >= 191) {
1045-
size_t exp_size;
1045+
const struct lfp_backlight_control_method *method;
10461046

1047-
if (i915->display.vbt.version >= 236)
1048-
exp_size = sizeof(struct bdb_lfp_backlight_data);
1049-
else if (i915->display.vbt.version >= 234)
1050-
exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_234;
1051-
else
1052-
exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_191;
1053-
1054-
if (get_blocksize(backlight_data) >= exp_size) {
1055-
const struct lfp_backlight_control_method *method;
1056-
1057-
method = &backlight_data->backlight_control[panel_type];
1058-
panel->vbt.backlight.type = method->type;
1059-
panel->vbt.backlight.controller = method->controller;
1060-
}
1047+
method = &backlight_data->backlight_control[panel_type];
1048+
panel->vbt.backlight.type = method->type;
1049+
panel->vbt.backlight.controller = method->controller;
10611050
}
10621051

10631052
panel->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;

‎drivers/gpu/drm/i915/display/intel_vbt_defs.h

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -897,11 +897,6 @@ struct lfp_brightness_level {
897897
u16 reserved;
898898
} __packed;
899899

900-
#define EXP_BDB_LFP_BL_DATA_SIZE_REV_191 \
901-
offsetof(struct bdb_lfp_backlight_data, brightness_level)
902-
#define EXP_BDB_LFP_BL_DATA_SIZE_REV_234 \
903-
offsetof(struct bdb_lfp_backlight_data, brightness_precision_bits)
904-
905900
struct bdb_lfp_backlight_data {
906901
u8 entry_size;
907902
struct lfp_backlight_data_entry data[16];

‎drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,14 +8,14 @@
88
#include "intel_gt_ccs_mode.h"
99
#include "intel_gt_regs.h"
1010

11-
void intel_gt_apply_ccs_mode(struct intel_gt *gt)
11+
unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt)
1212
{
1313
int cslice;
1414
u32 mode = 0;
1515
int first_ccs = __ffs(CCS_MASK(gt));
1616

1717
if (!IS_DG2(gt->i915))
18-
return;
18+
return 0;
1919

2020
/* Build the value for the fixed CCS load balancing */
2121
for (cslice = 0; cslice < I915_MAX_CCS; cslice++) {
@@ -35,5 +35,5 @@ void intel_gt_apply_ccs_mode(struct intel_gt *gt)
3535
XEHP_CCS_MODE_CSLICE_MASK);
3636
}
3737

38-
intel_uncore_write(gt->uncore, XEHP_CCS_MODE, mode);
38+
return mode;
3939
}

‎drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,6 @@
88

99
struct intel_gt;
1010

11-
void intel_gt_apply_ccs_mode(struct intel_gt *gt);
11+
unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt);
1212

1313
#endif /* __INTEL_GT_CCS_MODE_H__ */

‎drivers/gpu/drm/i915/gt/intel_workarounds.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2859,6 +2859,7 @@ add_render_compute_tuning_settings(struct intel_gt *gt,
28592859
static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal)
28602860
{
28612861
struct intel_gt *gt = engine->gt;
2862+
u32 mode;
28622863

28632864
if (!IS_DG2(gt->i915))
28642865
return;
@@ -2875,7 +2876,8 @@ static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_li
28752876
* After having disabled automatic load balancing we need to
28762877
* assign all slices to a single CCS. We will call it CCS mode 1
28772878
*/
2878-
intel_gt_apply_ccs_mode(gt);
2879+
mode = intel_gt_apply_ccs_mode(gt);
2880+
wa_masked_en(wal, XEHP_CCS_MODE, mode);
28792881
}
28802882

28812883
/*

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