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clk: starfive: Add StarFive JH7110 always-on clock driver
Add driver for the StarFive JH7110 always-on clock controller and register an auxiliary device for always-on reset controller which is named as "rst-aon". Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Co-developed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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‎drivers/clk/starfive/Kconfig

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@@ -31,3 +31,14 @@ config CLK_STARFIVE_JH7110_SYS
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help
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Say yes here to support the system clock controller on the
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StarFive JH7110 SoC.
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config CLK_STARFIVE_JH7110_AON
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tristate "StarFive JH7110 always-on clock support"
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depends on CLK_STARFIVE_JH7110_SYS
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select AUXILIARY_BUS
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select CLK_STARFIVE_JH71X0
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select RESET_STARFIVE_JH7110
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default m if ARCH_STARFIVE
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help
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Say yes here to support the always-on clock controller on the
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StarFive JH7110 SoC.

‎drivers/clk/starfive/Makefile

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@@ -5,3 +5,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o
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obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
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obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o
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obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o

‎drivers/clk/starfive/clk-starfive-jh7110-aon.c

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// SPDX-License-Identifier: GPL-2.0
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/*
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* StarFive JH7110 Always-On Clock Driver
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*
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* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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*/
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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#include "clk-starfive-jh7110.h"
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/* external clocks */
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#define JH7110_AONCLK_OSC (JH7110_AONCLK_END + 0)
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#define JH7110_AONCLK_GMAC0_RMII_REFIN (JH7110_AONCLK_END + 1)
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#define JH7110_AONCLK_GMAC0_RGMII_RXIN (JH7110_AONCLK_END + 2)
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#define JH7110_AONCLK_STG_AXIAHB (JH7110_AONCLK_END + 3)
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#define JH7110_AONCLK_APB_BUS (JH7110_AONCLK_END + 4)
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#define JH7110_AONCLK_GMAC0_GTXCLK (JH7110_AONCLK_END + 5)
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#define JH7110_AONCLK_RTC_OSC (JH7110_AONCLK_END + 6)
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static const struct jh71x0_clk_data jh7110_aonclk_data[] = {
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/* source */
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JH71X0__DIV(JH7110_AONCLK_OSC_DIV4, "osc_div4", 4, JH7110_AONCLK_OSC),
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JH71X0__MUX(JH7110_AONCLK_APB_FUNC, "apb_func", 2,
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JH7110_AONCLK_OSC_DIV4,
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JH7110_AONCLK_OSC),
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/* gmac0 */
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JH71X0_GATE(JH7110_AONCLK_GMAC0_AHB, "gmac0_ahb", 0, JH7110_AONCLK_STG_AXIAHB),
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JH71X0_GATE(JH7110_AONCLK_GMAC0_AXI, "gmac0_axi", 0, JH7110_AONCLK_STG_AXIAHB),
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JH71X0__DIV(JH7110_AONCLK_GMAC0_RMII_RTX, "gmac0_rmii_rtx", 30,
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JH7110_AONCLK_GMAC0_RMII_REFIN),
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JH71X0_GMUX(JH7110_AONCLK_GMAC0_TX, "gmac0_tx",
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2,
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JH7110_AONCLK_GMAC0_GTXCLK,
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JH7110_AONCLK_GMAC0_RMII_RTX),
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JH71X0__INV(JH7110_AONCLK_GMAC0_TX_INV, "gmac0_tx_inv", JH7110_AONCLK_GMAC0_TX),
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JH71X0__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 2,
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JH7110_AONCLK_GMAC0_RGMII_RXIN,
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JH7110_AONCLK_GMAC0_RMII_RTX),
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JH71X0__INV(JH7110_AONCLK_GMAC0_RX_INV, "gmac0_rx_inv", JH7110_AONCLK_GMAC0_RX),
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/* otpc */
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JH71X0_GATE(JH7110_AONCLK_OTPC_APB, "otpc_apb", 0, JH7110_AONCLK_APB_BUS),
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/* rtc */
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JH71X0_GATE(JH7110_AONCLK_RTC_APB, "rtc_apb", 0, JH7110_AONCLK_APB_BUS),
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JH71X0__DIV(JH7110_AONCLK_RTC_INTERNAL, "rtc_internal", 1022, JH7110_AONCLK_OSC),
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JH71X0__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 2,
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JH7110_AONCLK_RTC_OSC,
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JH7110_AONCLK_RTC_INTERNAL),
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JH71X0_GATE(JH7110_AONCLK_RTC_CAL, "rtc_cal", 0, JH7110_AONCLK_OSC),
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};
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static struct clk_hw *jh7110_aonclk_get(struct of_phandle_args *clkspec, void *data)
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{
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struct jh71x0_clk_priv *priv = data;
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unsigned int idx = clkspec->args[0];
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if (idx < JH7110_AONCLK_END)
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return &priv->reg[idx].hw;
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return ERR_PTR(-EINVAL);
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}
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static int jh7110_aoncrg_probe(struct platform_device *pdev)
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{
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struct jh71x0_clk_priv *priv;
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unsigned int idx;
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int ret;
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priv = devm_kzalloc(&pdev->dev,
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struct_size(priv, reg, JH7110_AONCLK_END),
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GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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spin_lock_init(&priv->rmw_lock);
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priv->dev = &pdev->dev;
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priv->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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dev_set_drvdata(priv->dev, (void *)(&priv->base));
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for (idx = 0; idx < JH7110_AONCLK_END; idx++) {
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u32 max = jh7110_aonclk_data[idx].max;
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struct clk_parent_data parents[4] = {};
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struct clk_init_data init = {
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.name = jh7110_aonclk_data[idx].name,
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.ops = starfive_jh71x0_clk_ops(max),
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.parent_data = parents,
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.num_parents =
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((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
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.flags = jh7110_aonclk_data[idx].flags,
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};
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struct jh71x0_clk *clk = &priv->reg[idx];
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unsigned int i;
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for (i = 0; i < init.num_parents; i++) {
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unsigned int pidx = jh7110_aonclk_data[idx].parents[i];
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if (pidx < JH7110_AONCLK_END)
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parents[i].hw = &priv->reg[pidx].hw;
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else if (pidx == JH7110_AONCLK_OSC)
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parents[i].fw_name = "osc";
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else if (pidx == JH7110_AONCLK_GMAC0_RMII_REFIN)
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parents[i].fw_name = "gmac0_rmii_refin";
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else if (pidx == JH7110_AONCLK_GMAC0_RGMII_RXIN)
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parents[i].fw_name = "gmac0_rgmii_rxin";
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else if (pidx == JH7110_AONCLK_STG_AXIAHB)
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parents[i].fw_name = "stg_axiahb";
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else if (pidx == JH7110_AONCLK_APB_BUS)
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parents[i].fw_name = "apb_bus";
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else if (pidx == JH7110_AONCLK_GMAC0_GTXCLK)
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parents[i].fw_name = "gmac0_gtxclk";
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else if (pidx == JH7110_AONCLK_RTC_OSC)
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parents[i].fw_name = "rtc_osc";
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}
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clk->hw.init = &init;
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clk->idx = idx;
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clk->max_div = max & JH71X0_CLK_DIV_MASK;
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ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
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if (ret)
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return ret;
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}
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ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_aonclk_get, priv);
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if (ret)
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return ret;
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return jh7110_reset_controller_register(priv, "rst-aon", 1);
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}
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static const struct of_device_id jh7110_aoncrg_match[] = {
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{ .compatible = "starfive,jh7110-aoncrg" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, jh7110_aoncrg_match);
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static struct platform_driver jh7110_aoncrg_driver = {
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.probe = jh7110_aoncrg_probe,
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.driver = {
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.name = "clk-starfive-jh7110-aon",
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.of_match_table = jh7110_aoncrg_match,
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},
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};
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module_platform_driver(jh7110_aoncrg_driver);
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MODULE_AUTHOR("Emil Renner Berthing");
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MODULE_DESCRIPTION("StarFive JH7110 always-on clock driver");
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MODULE_LICENSE("GPL");

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