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| 1 | +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/interconnect/qcom,sar2130p-rpmh.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: Qualcomm RPMh Network-On-Chip Interconnect on SAR2130P |
| 8 | + |
| 9 | +maintainers: |
| 10 | + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
| 11 | + - Georgi Djakov <djakov@kernel.org> |
| 12 | + |
| 13 | +description: | |
| 14 | + RPMh interconnect providers support system bandwidth requirements through |
| 15 | + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is |
| 16 | + able to communicate with the BCM through the Resource State Coordinator (RSC) |
| 17 | + associated with each execution environment. Provider nodes must point to at |
| 18 | + least one RPMh device child node pertaining to their RSC and each provider |
| 19 | + can map to multiple RPMh resources. |
| 20 | +
|
| 21 | + See also:: include/dt-bindings/interconnect/qcom,sar2130p-rpmh.h |
| 22 | +
|
| 23 | +properties: |
| 24 | + compatible: |
| 25 | + enum: |
| 26 | + - qcom,sar2130p-clk-virt |
| 27 | + - qcom,sar2130p-config-noc |
| 28 | + - qcom,sar2130p-gem-noc |
| 29 | + - qcom,sar2130p-lpass-ag-noc |
| 30 | + - qcom,sar2130p-mc-virt |
| 31 | + - qcom,sar2130p-mmss-noc |
| 32 | + - qcom,sar2130p-nsp-noc |
| 33 | + - qcom,sar2130p-pcie-anoc |
| 34 | + - qcom,sar2130p-system-noc |
| 35 | + |
| 36 | + reg: |
| 37 | + maxItems: 1 |
| 38 | + |
| 39 | + clocks: |
| 40 | + minItems: 1 |
| 41 | + maxItems: 2 |
| 42 | + |
| 43 | +required: |
| 44 | + - compatible |
| 45 | + |
| 46 | +allOf: |
| 47 | + - $ref: qcom,rpmh-common.yaml# |
| 48 | + - if: |
| 49 | + properties: |
| 50 | + compatible: |
| 51 | + contains: |
| 52 | + enum: |
| 53 | + - qcom,sar2130p-clk-virt |
| 54 | + - qcom,sar2130p-mc-virt |
| 55 | + then: |
| 56 | + properties: |
| 57 | + reg: false |
| 58 | + else: |
| 59 | + required: |
| 60 | + - reg |
| 61 | + |
| 62 | + - if: |
| 63 | + properties: |
| 64 | + compatible: |
| 65 | + contains: |
| 66 | + enum: |
| 67 | + - qcom,sar2130p-pcie-anoc |
| 68 | + then: |
| 69 | + properties: |
| 70 | + clocks: |
| 71 | + items: |
| 72 | + - description: aggre-NOC PCIe AXI clock |
| 73 | + - description: cfg-NOC PCIe a-NOC AHB clock |
| 74 | + |
| 75 | + - if: |
| 76 | + properties: |
| 77 | + compatible: |
| 78 | + contains: |
| 79 | + enum: |
| 80 | + - qcom,sar2130p-system-noc |
| 81 | + then: |
| 82 | + properties: |
| 83 | + clocks: |
| 84 | + items: |
| 85 | + - description: aggre USB3 PRIM AXI clock |
| 86 | + |
| 87 | + - if: |
| 88 | + properties: |
| 89 | + compatible: |
| 90 | + contains: |
| 91 | + enum: |
| 92 | + - qcom,sar2130p-system-noc |
| 93 | + - qcom,sar2130p-pcie-anoc |
| 94 | + then: |
| 95 | + required: |
| 96 | + - clocks |
| 97 | + else: |
| 98 | + properties: |
| 99 | + clocks: false |
| 100 | + |
| 101 | +unevaluatedProperties: false |
| 102 | + |
| 103 | +examples: |
| 104 | + - | |
| 105 | + clk_virt: interconnect-0 { |
| 106 | + compatible = "qcom,sar2130p-clk-virt"; |
| 107 | + #interconnect-cells = <2>; |
| 108 | + qcom,bcm-voters = <&apps_bcm_voter>; |
| 109 | + }; |
| 110 | +
|
| 111 | + aggre1_noc: interconnect@1680000 { |
| 112 | + compatible = "qcom,sar2130p-system-noc"; |
| 113 | + reg = <0x01680000 0x29080>; |
| 114 | + #interconnect-cells = <2>; |
| 115 | + clocks = <&gcc_prim_axi_clk>; |
| 116 | + qcom,bcm-voters = <&apps_bcm_voter>; |
| 117 | + }; |
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