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airliedairlied
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Merge tag 'drm-intel-next-2024-02-07' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
drm/i915 feature pull for v6.9: Features and functionality: - Early transport for panel replay and PSR (Jouni) - New ARL PCI IDs (Matt) - DP TPS4 PHY test pattern support (Khaled) Refactoring and cleanups: - Unify and improve VSC SDP for PSR and non-PSR cases (Jouni) - Refactor memory regions and improve debug logging (Ville) - Rework global state serialization (Ville) - Remove unused CDCLK divider fields (Gustavo) - Unify HDCP connector logging format (Jani) - Use display instead of graphics version in display code (Jani) - Move VBT and opregion debugfs next to the implementation (Jani) - Abstract opregion interface, use opaque type (Jani) Fixes: - Fix MTL stolen memory access (Ville) - Fix initial display plane readout for MTL (Ville) - Fix HPD handling during driver init/shutdown (Imre) - Cursor vblank evasion fixes (Ville) - Various VSC SDP fixes (Jouni) - Allow PSR mode changes without full modeset (Jouni) - Fix CDCLK sanitization on module load for Xe2_LPD (Gustavo) - Fix the max DSC bpc supported by the source (Ankit) - Add missing LNL ALPM AUX wake configuration (Jouni) - Cx0 PHY state readout and verify fixes (Mika) - Fix PSR (panel replay) debugfs for MST connectors (Imre) - Fail HDCP repeater authentication if Type1 device not present (Suraj) - Ratelimit debug logging in vm_fault_ttm (Nirmoy) - Use a fake PCH for MTL because south display is not on the PCH (Haridhar) - Disable DSB for Xe driver for now (José) - Fix some LNL display register changes (Lucas) - Fix build on ChromeOS (Paz Zcharya) - Preserve current shared DPLL for fastsets on Type-C ports (Ville) - Fix state checker warnings for MG/TC/TBT PLLs (Ville) - Fix HDCP repeater ctl register value on errors (Jani) - Allow FBC with CCS modifiers on SKL+ (Ville) - Fix HDCP GGTT pinning (Ville) DRM core changes: - Add ratelimited drm dbg print (Nirmoy) - DPCD PSR early transport macro (Jouni) Merges: - Backmerge drm-next to bring Xe driver to drm-intel-next (Jani) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/87cyt8cxsh.fsf@intel.com
2 parents b344e64 + 449c2d5 commit b13cfb4

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‎drivers/gpu/drm/i915/display/i9xx_plane.c

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1060,3 +1060,33 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
10601060

10611061
plane_config->fb = intel_fb;
10621062
}
1063+
1064+
bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc,
1065+
const struct intel_initial_plane_config *plane_config)
1066+
{
1067+
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1068+
struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1069+
const struct intel_plane_state *plane_state =
1070+
to_intel_plane_state(plane->base.state);
1071+
enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
1072+
u32 base;
1073+
1074+
if (!plane_state->uapi.visible)
1075+
return false;
1076+
1077+
base = intel_plane_ggtt_offset(plane_state);
1078+
1079+
/*
1080+
* We may have moved the surface to a different
1081+
* part of ggtt, make the plane aware of that.
1082+
*/
1083+
if (plane_config->base == base)
1084+
return false;
1085+
1086+
if (DISPLAY_VER(dev_priv) >= 4)
1087+
intel_de_write(dev_priv, DSPSURF(i9xx_plane), base);
1088+
else
1089+
intel_de_write(dev_priv, DSPADDR(i9xx_plane), base);
1090+
1091+
return true;
1092+
}

‎drivers/gpu/drm/i915/display/i9xx_plane.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,8 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe);
2626

2727
void i9xx_get_initial_plane_config(struct intel_crtc *crtc,
2828
struct intel_initial_plane_config *plane_config);
29+
bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc,
30+
const struct intel_initial_plane_config *plane_config);
2931
#else
3032
static inline unsigned int i965_plane_max_stride(struct intel_plane *plane,
3133
u32 pixel_format, u64 modifier,
@@ -46,6 +48,11 @@ static inline void i9xx_get_initial_plane_config(struct intel_crtc *crtc,
4648
struct intel_initial_plane_config *plane_config)
4749
{
4850
}
51+
static inline bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc,
52+
const struct intel_initial_plane_config *plane_config)
53+
{
54+
return false;
55+
}
4956
#endif
5057

5158
#endif

‎drivers/gpu/drm/i915/display/intel_atomic_plane.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -217,6 +217,9 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
217217
int width, height;
218218
unsigned int rel_data_rate;
219219

220+
if (plane->id == PLANE_CURSOR)
221+
return 0;
222+
220223
if (!plane_state->uapi.visible)
221224
return 0;
222225

@@ -244,9 +247,6 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
244247

245248
rel_data_rate = width * height * fb->format->cpp[color_plane];
246249

247-
if (plane->id == PLANE_CURSOR)
248-
return rel_data_rate;
249-
250250
return intel_adjusted_rate(&plane_state->uapi.src,
251251
&plane_state->uapi.dst,
252252
rel_data_rate);

‎drivers/gpu/drm/i915/display/intel_backlight.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1465,7 +1465,7 @@ static bool cnp_backlight_controller_is_valid(struct drm_i915_private *i915, int
14651465

14661466
if (controller == 1 &&
14671467
INTEL_PCH_TYPE(i915) >= PCH_ICP &&
1468-
INTEL_PCH_TYPE(i915) < PCH_MTP)
1468+
INTEL_PCH_TYPE(i915) <= PCH_ADP)
14691469
return intel_de_read(i915, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT;
14701470

14711471
return true;

‎drivers/gpu/drm/i915/display/intel_bios.c

Lines changed: 32 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2204,8 +2204,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin)
22042204
if (IS_DGFX(i915))
22052205
return vbt_pin;
22062206

2207-
if (INTEL_PCH_TYPE(i915) >= PCH_LNL || HAS_PCH_MTP(i915) ||
2208-
IS_ALDERLAKE_P(i915)) {
2207+
if (INTEL_PCH_TYPE(i915) >= PCH_MTL || IS_ALDERLAKE_P(i915)) {
22092208
ddc_pin_map = adlp_ddc_pin_map;
22102209
n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
22112210
} else if (IS_ALDERLAKE_S(i915)) {
@@ -3074,7 +3073,7 @@ static struct vbt_header *oprom_get_vbt(struct drm_i915_private *i915)
30743073
*/
30753074
void intel_bios_init(struct drm_i915_private *i915)
30763075
{
3077-
const struct vbt_header *vbt = i915->display.opregion.vbt;
3076+
const struct vbt_header *vbt;
30783077
struct vbt_header *oprom_vbt = NULL;
30793078
const struct bdb_header *bdb;
30803079

@@ -3089,6 +3088,8 @@ void intel_bios_init(struct drm_i915_private *i915)
30893088

30903089
init_vbt_defaults(i915);
30913090

3091+
vbt = intel_opregion_get_vbt(i915, NULL);
3092+
30923093
/*
30933094
* If the OpRegion does not have VBT, look in SPI flash through MMIO or
30943095
* PCI mapping
@@ -3306,7 +3307,7 @@ bool intel_bios_is_lvds_present(struct drm_i915_private *i915, u8 *i2c_pin)
33063307
* additional data. Trust that if the VBT was written into
33073308
* the OpRegion then they have validated the LVDS's existence.
33083309
*/
3309-
if (i915->display.opregion.vbt)
3310+
if (intel_opregion_get_vbt(i915, NULL))
33103311
return true;
33113312
}
33123313

@@ -3657,3 +3658,30 @@ void intel_bios_for_each_encoder(struct drm_i915_private *i915,
36573658
list_for_each_entry(devdata, &i915->display.vbt.display_devices, node)
36583659
func(i915, devdata);
36593660
}
3661+
3662+
static int intel_bios_vbt_show(struct seq_file *m, void *unused)
3663+
{
3664+
struct drm_i915_private *i915 = m->private;
3665+
const void *vbt;
3666+
size_t vbt_size;
3667+
3668+
/*
3669+
* FIXME: VBT might originate from other places than opregion, and then
3670+
* this would be incorrect.
3671+
*/
3672+
vbt = intel_opregion_get_vbt(i915, &vbt_size);
3673+
if (vbt)
3674+
seq_write(m, vbt, vbt_size);
3675+
3676+
return 0;
3677+
}
3678+
3679+
DEFINE_SHOW_ATTRIBUTE(intel_bios_vbt);
3680+
3681+
void intel_bios_debugfs_register(struct drm_i915_private *i915)
3682+
{
3683+
struct drm_minor *minor = i915->drm.primary;
3684+
3685+
debugfs_create_file("i915_vbt", 0444, minor->debugfs_root,
3686+
i915, &intel_bios_vbt_fops);
3687+
}

‎drivers/gpu/drm/i915/display/intel_bios.h

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -246,13 +246,10 @@ bool intel_bios_is_valid_vbt(const void *buf, size_t size);
246246
bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
247247
bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
248248
bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
249-
bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
250249
bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
251250
bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
252251
struct intel_crtc_state *crtc_state,
253252
int dsc_max_bpc);
254-
bool intel_bios_port_supports_typec_usb(struct drm_i915_private *i915, enum port port);
255-
bool intel_bios_port_supports_tbt(struct drm_i915_private *i915, enum port port);
256253

257254
const struct intel_bios_encoder_data *
258255
intel_bios_encoder_data_lookup(struct drm_i915_private *i915, enum port port);
@@ -283,4 +280,6 @@ void intel_bios_for_each_encoder(struct drm_i915_private *i915,
283280
void (*func)(struct drm_i915_private *i915,
284281
const struct intel_bios_encoder_data *devdata));
285282

283+
void intel_bios_debugfs_register(struct drm_i915_private *i915);
284+
286285
#endif /* _INTEL_BIOS_H_ */

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