@@ -240,25 +240,25 @@ enum ipa_reg_local_pkt_proc_cntxt_field_id {
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/* COUNTER_CFG register */
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enum ipa_reg_counter_cfg_field_id {
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- EOT_COAL_GRANULARITY , /* Not v3.5+ */
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+ EOT_COAL_GRANULARITY , /* Not IPA v3.5+ */
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AGGR_GRANULARITY ,
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};
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/* IPA_TX_CFG register */
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enum ipa_reg_ipa_tx_cfg_field_id {
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- TX0_PREFETCH_DISABLE , /* Not v4.0+ */
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- TX1_PREFETCH_DISABLE , /* Not v4.0+ */
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- PREFETCH_ALMOST_EMPTY_SIZE , /* Not v4.0+ */
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- PREFETCH_ALMOST_EMPTY_SIZE_TX0 , /* v4.0+ */
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- DMAW_SCND_OUTSD_PRED_THRESHOLD , /* v4.0+ */
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- DMAW_SCND_OUTSD_PRED_EN , /* v4.0+ */
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- DMAW_MAX_BEATS_256_DIS , /* v4.0+ */
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- PA_MASK_EN , /* v4.0+ */
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- PREFETCH_ALMOST_EMPTY_SIZE_TX1 , /* v4.0+ */
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- DUAL_TX_ENABLE , /* v4.5+ */
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- SSPND_PA_NO_START_STATE , /* v4,2+, not v4.5 */
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- SSPND_PA_NO_BQ_STATE , /* v4.2 only */
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- HOLB_STICKY_DROP_EN , /* v5.0+ */
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+ TX0_PREFETCH_DISABLE , /* Not IPA v4.0+ */
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+ TX1_PREFETCH_DISABLE , /* Not IPA v4.0+ */
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+ PREFETCH_ALMOST_EMPTY_SIZE , /* Not IPA v4.0+ */
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+ PREFETCH_ALMOST_EMPTY_SIZE_TX0 , /* IPA v4.0+ */
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+ DMAW_SCND_OUTSD_PRED_THRESHOLD , /* IPA v4.0+ */
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+ DMAW_SCND_OUTSD_PRED_EN , /* IPA v4.0+ */
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+ DMAW_MAX_BEATS_256_DIS , /* IPA v4.0+ */
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+ PA_MASK_EN , /* IPA v4.0+ */
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+ PREFETCH_ALMOST_EMPTY_SIZE_TX1 , /* IPA v4.0+ */
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+ DUAL_TX_ENABLE , /* IPA v4.5+ */
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+ SSPND_PA_NO_START_STATE , /* IPA v4,2+, not IPA v4.5 */
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+ SSPND_PA_NO_BQ_STATE , /* IPA v4.2 only */
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+ HOLB_STICKY_DROP_EN , /* IPA v5.0+ */
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};
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/* FLAVOR_0 register */
@@ -319,8 +319,8 @@ enum ipa_reg_rsrc_grp_rsrc_type_field_id {
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/* ENDP_INIT_CTRL register */
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enum ipa_reg_endp_init_ctrl_field_id {
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- ENDP_SUSPEND , /* Not v4.0+ */
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- ENDP_DELAY , /* Not v4.2+ */
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+ ENDP_SUSPEND , /* Not IPA v4.0+ */
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+ ENDP_DELAY , /* Not IPA v4.2+ */
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};
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/* ENDP_INIT_CFG register */
@@ -359,11 +359,11 @@ enum ipa_reg_endp_init_hdr_field_id {
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HDR_ADDITIONAL_CONST_LEN ,
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HDR_OFST_PKT_SIZE_VALID ,
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HDR_OFST_PKT_SIZE ,
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- HDR_A5_MUX , /* Not v4.9+ */
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+ HDR_A5_MUX , /* Not IPA v4.9+ */
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HDR_LEN_INC_DEAGG_HDR ,
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- HDR_METADATA_REG_VALID , /* Not v4.5+ */
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- HDR_LEN_MSB , /* v4.5+ */
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- HDR_OFST_METADATA_MSB , /* v4.5+ */
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+ HDR_METADATA_REG_VALID , /* Not IPA v4.5+ */
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+ HDR_LEN_MSB , /* IPA v4.5+ */
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+ HDR_OFST_METADATA_MSB , /* IPA v4.5+ */
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};
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/* ENDP_INIT_HDR_EXT register */
@@ -374,23 +374,23 @@ enum ipa_reg_endp_init_hdr_ext_field_id {
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HDR_PAYLOAD_LEN_INC_PADDING ,
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HDR_TOTAL_LEN_OR_PAD_OFFSET ,
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HDR_PAD_TO_ALIGNMENT ,
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- HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB , /* v4.5+ */
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- HDR_OFST_PKT_SIZE_MSB , /* v4.5+ */
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- HDR_ADDITIONAL_CONST_LEN_MSB , /* v4.5+ */
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- HDR_BYTES_TO_REMOVE_VALID , /* v5.0+ */
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- HDR_BYTES_TO_REMOVE , /* v5.0+ */
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+ HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB , /* IPA v4.5+ */
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+ HDR_OFST_PKT_SIZE_MSB , /* IPA v4.5+ */
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+ HDR_ADDITIONAL_CONST_LEN_MSB , /* IPA v4.5+ */
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+ HDR_BYTES_TO_REMOVE_VALID , /* IPA v5.0+ */
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+ HDR_BYTES_TO_REMOVE , /* IPA v5.0+ */
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};
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/* ENDP_INIT_MODE register */
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enum ipa_reg_endp_init_mode_field_id {
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ENDP_MODE ,
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- DCPH_ENABLE , /* v4.5+ */
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+ DCPH_ENABLE , /* IPA v4.5+ */
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DEST_PIPE_INDEX ,
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BYTE_THRESHOLD ,
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PIPE_REPLICATION_EN ,
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PAD_EN ,
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- HDR_FTCH_DISABLE , /* v4.5+ */
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- DRBIP_ACL_ENABLE , /* v4.9+ */
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+ HDR_FTCH_DISABLE , /* IPA v4.5+ */
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+ DRBIP_ACL_ENABLE , /* IPA v4.9+ */
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};
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/** enum ipa_mode - ENDP_INIT_MODE register MODE field value */
@@ -439,10 +439,10 @@ enum ipa_reg_endp_init_hol_block_en_field_id {
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/* ENDP_INIT_HOL_BLOCK_TIMER register */
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enum ipa_reg_endp_init_hol_block_timer_field_id {
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- TIMER_BASE_VALUE , /* Not v4.5+ */
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- TIMER_SCALE , /* v4.2 only */
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- TIMER_LIMIT , /* v4.5+ */
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- TIMER_GRAN_SEL , /* v4.5+ */
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+ TIMER_BASE_VALUE , /* Not IPA v4.5+ */
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+ TIMER_SCALE , /* IPA v4.2 only */
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+ TIMER_LIMIT , /* IPA v4.5+ */
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+ TIMER_GRAN_SEL , /* IPA v4.5+ */
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};
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/* ENDP_INIT_DEAGGR register */
@@ -463,7 +463,7 @@ enum ipa_reg_endp_init_rsrc_grp_field_id {
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/* ENDP_INIT_SEQ register */
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enum ipa_reg_endp_init_seq_field_id {
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SEQ_TYPE ,
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- SEQ_REP_TYPE , /* Not v4.5+ */
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+ SEQ_REP_TYPE , /* Not IPA v4.5+ */
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};
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/**
@@ -512,8 +512,8 @@ enum ipa_seq_rep_type {
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enum ipa_reg_endp_status_field_id {
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STATUS_EN ,
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STATUS_ENDP ,
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- STATUS_LOCATION , /* Not v4.5+ */
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- STATUS_PKT_SUPPRESS , /* v4.0+ */
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+ STATUS_LOCATION , /* Not IPA v4.5+ */
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+ STATUS_PKT_SUPPRESS , /* IPA v4.0+ */
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};
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/* ENDP_FILTER_ROUTER_HSH_CFG register */
@@ -588,8 +588,7 @@ enum ipa_reg_endp_cache_cfg_field_id {
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*/
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enum ipa_irq_id {
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IPA_IRQ_BAD_SNOC_ACCESS = 0x0 ,
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- /* The next bit is not present for IPA v3.5+ */
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- IPA_IRQ_EOT_COAL = 0x1 ,
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+ IPA_IRQ_EOT_COAL = 0x1 , /* Not IPA v3.5+ */
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IPA_IRQ_UC_0 = 0x2 ,
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IPA_IRQ_UC_1 = 0x3 ,
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IPA_IRQ_UC_2 = 0x4 ,
@@ -610,17 +609,14 @@ enum ipa_irq_id {
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IPA_IRQ_PIPE_YELLOW_ABOVE = 0x13 ,
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IPA_IRQ_PIPE_RED_ABOVE = 0x14 ,
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IPA_IRQ_UCP = 0x15 ,
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- /* The next bit is not present for IPA v4.5+ */
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- IPA_IRQ_DCMP = 0x16 ,
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+ IPA_IRQ_DCMP = 0x16 , /* Not IPA v4.5+ */
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IPA_IRQ_GSI_EE = 0x17 ,
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IPA_IRQ_GSI_IPA_IF_TLV_RCVD = 0x18 ,
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IPA_IRQ_GSI_UC = 0x19 ,
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- /* The next bit is present for IPA v4.5+ */
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- IPA_IRQ_TLV_LEN_MIN_DSM = 0x1a ,
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- /* The next three bits are present for IPA v4.9+ */
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- IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN = 0x1b ,
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- IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN = 0x1c ,
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- IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN = 0x1d ,
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+ IPA_IRQ_TLV_LEN_MIN_DSM = 0x1a , /* IPA v4.5+ */
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+ IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN = 0x1b , /* IPA v4.9+ */
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+ IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN = 0x1c , /* IPA v4.9+ */
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+ IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN = 0x1d , /* IPA v4.9+ */
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IPA_IRQ_COUNT , /* Last; not an id */
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};
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