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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd: "A bunch of clk driver fixes for issues found recently: - Fix the binding for versaclock3 that was introduced this merge window so we know what the values are for clk consumers - Fix a 64-bit division issue in the versaclock3 driver - Avoid breakage in the versaclock3 driver by rejiggering the enums used to layout clks - Fix the parent name of a clk in the Spreadtrum ums512 clk driver - Fix a suspend/resume issue in Skyworks Si521xx clk driver where regmap restoration fails because writes are wedged - Return zero from Tegra bpmp recalc_rate() implementation when an error occurs so we don't consider an error as a large rate" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: tegra: fix error return case for recalc_rate clk: si521xx: Fix regmap write accessor clk: si521xx: Use REGCACHE_FLAT instead of NONE clk: sprd: Fix thm_parents incorrect configuration clk: vc3: Make vc3_clk_mux enum values based on vc3_clk enum values clk: vc3: Fix output clock mapping clk: vc3: Fix 64 by 64 division dt-bindings: clock: versaclock3: Add description for #clock-cells property
2 parents 94b7ed3 + a47b44f commit acfdcae

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-51
lines changed

5 files changed

+54
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lines changed

‎Documentation/devicetree/bindings/clock/renesas,5p35023.yaml

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,9 @@ properties:
3737
maxItems: 1
3838

3939
'#clock-cells':
40+
description:
41+
The index in the assigned-clocks is mapped to the output clock as below
42+
0 - REF, 1 - SE1, 2 - SE2, 3 - SE3, 4 - DIFF1, 5 - DIFF2.
4043
const: 1
4144

4245
clocks:
@@ -68,7 +71,7 @@ examples:
6871
reg = <0x68>;
6972
#clock-cells = <1>;
7073
71-
clocks = <&x1_x2>;
74+
clocks = <&x1>;
7275
7376
renesas,settings = [
7477
80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
@@ -79,8 +82,8 @@ examples:
7982
assigned-clocks = <&versa3 0>, <&versa3 1>,
8083
<&versa3 2>, <&versa3 3>,
8184
<&versa3 4>, <&versa3 5>;
82-
assigned-clock-rates = <12288000>, <25000000>,
83-
<12000000>, <11289600>,
84-
<11289600>, <24000000>;
85+
assigned-clock-rates = <24000000>, <11289600>,
86+
<11289600>, <12000000>,
87+
<25000000>, <12288000>;
8588
};
8689
};

‎drivers/clk/clk-si521xx.c

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -96,7 +96,7 @@ static int si521xx_regmap_i2c_write(void *context, unsigned int reg,
9696
unsigned int val)
9797
{
9898
struct i2c_client *i2c = context;
99-
const u8 data[3] = { reg, 1, val };
99+
const u8 data[2] = { reg, val };
100100
const int count = ARRAY_SIZE(data);
101101
int ret;
102102

@@ -146,7 +146,7 @@ static int si521xx_regmap_i2c_read(void *context, unsigned int reg,
146146
static const struct regmap_config si521xx_regmap_config = {
147147
.reg_bits = 8,
148148
.val_bits = 8,
149-
.cache_type = REGCACHE_NONE,
149+
.cache_type = REGCACHE_FLAT,
150150
.max_register = SI521XX_REG_DA,
151151
.rd_table = &si521xx_readable_table,
152152
.wr_table = &si521xx_writeable_table,
@@ -281,9 +281,10 @@ static int si521xx_probe(struct i2c_client *client)
281281
{
282282
const u16 chip_info = (u16)(uintptr_t)device_get_match_data(&client->dev);
283283
const struct clk_parent_data clk_parent_data = { .index = 0 };
284-
struct si521xx *si;
284+
const u8 data[3] = { SI521XX_REG_BC, 1, 1 };
285285
unsigned char name[6] = "DIFF0";
286286
struct clk_init_data init = {};
287+
struct si521xx *si;
287288
int i, ret;
288289

289290
if (!chip_info)
@@ -308,7 +309,7 @@ static int si521xx_probe(struct i2c_client *client)
308309
"Failed to allocate register map\n");
309310

310311
/* Always read back 1 Byte via I2C */
311-
ret = regmap_write(si->regmap, SI521XX_REG_BC, 1);
312+
ret = i2c_master_send(client, data, ARRAY_SIZE(data));
312313
if (ret < 0)
313314
return ret;
314315

‎drivers/clk/clk-versaclock3.c

Lines changed: 40 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -118,21 +118,21 @@ enum vc3_div {
118118
VC3_DIV5,
119119
};
120120

121-
enum vc3_clk_mux {
122-
VC3_DIFF2_MUX,
123-
VC3_DIFF1_MUX,
124-
VC3_SE3_MUX,
125-
VC3_SE2_MUX,
126-
VC3_SE1_MUX,
127-
};
128-
129121
enum vc3_clk {
130-
VC3_DIFF2,
131-
VC3_DIFF1,
132-
VC3_SE3,
133-
VC3_SE2,
134-
VC3_SE1,
135122
VC3_REF,
123+
VC3_SE1,
124+
VC3_SE2,
125+
VC3_SE3,
126+
VC3_DIFF1,
127+
VC3_DIFF2,
128+
};
129+
130+
enum vc3_clk_mux {
131+
VC3_SE1_MUX = VC3_SE1 - 1,
132+
VC3_SE2_MUX = VC3_SE2 - 1,
133+
VC3_SE3_MUX = VC3_SE3 - 1,
134+
VC3_DIFF1_MUX = VC3_DIFF1 - 1,
135+
VC3_DIFF2_MUX = VC3_DIFF2 - 1,
136136
};
137137

138138
struct vc3_clk_data {
@@ -401,11 +401,10 @@ static long vc3_pll_round_rate(struct clk_hw *hw, unsigned long rate,
401401
/* Determine best fractional part, which is 16 bit wide */
402402
div_frc = rate % *parent_rate;
403403
div_frc *= BIT(16) - 1;
404-
do_div(div_frc, *parent_rate);
405404

406-
vc3->div_frc = (u32)div_frc;
405+
vc3->div_frc = min_t(u64, div64_ul(div_frc, *parent_rate), U16_MAX);
407406
rate = (*parent_rate *
408-
(vc3->div_int * VC3_2_POW_16 + div_frc) / VC3_2_POW_16);
407+
(vc3->div_int * VC3_2_POW_16 + vc3->div_frc) / VC3_2_POW_16);
409408
} else {
410409
rate = *parent_rate * vc3->div_int;
411410
}
@@ -897,33 +896,33 @@ static struct vc3_hw_data clk_div[] = {
897896
};
898897

899898
static struct vc3_hw_data clk_mux[] = {
900-
[VC3_DIFF2_MUX] = {
899+
[VC3_SE1_MUX] = {
901900
.data = &(struct vc3_clk_data) {
902-
.offs = VC3_DIFF2_CTRL_REG,
903-
.bitmsk = VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL
901+
.offs = VC3_SE1_DIV4_CTRL,
902+
.bitmsk = VC3_SE1_DIV4_CTRL_SE1_CLK_SEL
904903
},
905904
.hw.init = &(struct clk_init_data){
906-
.name = "diff2_mux",
905+
.name = "se1_mux",
907906
.ops = &vc3_clk_mux_ops,
908907
.parent_hws = (const struct clk_hw *[]) {
909-
&clk_div[VC3_DIV1].hw,
910-
&clk_div[VC3_DIV3].hw
908+
&clk_div[VC3_DIV5].hw,
909+
&clk_div[VC3_DIV4].hw
911910
},
912911
.num_parents = 2,
913912
.flags = CLK_SET_RATE_PARENT
914913
}
915914
},
916-
[VC3_DIFF1_MUX] = {
915+
[VC3_SE2_MUX] = {
917916
.data = &(struct vc3_clk_data) {
918-
.offs = VC3_DIFF1_CTRL_REG,
919-
.bitmsk = VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL
917+
.offs = VC3_SE2_CTRL_REG0,
918+
.bitmsk = VC3_SE2_CTRL_REG0_SE2_CLK_SEL
920919
},
921920
.hw.init = &(struct clk_init_data){
922-
.name = "diff1_mux",
921+
.name = "se2_mux",
923922
.ops = &vc3_clk_mux_ops,
924923
.parent_hws = (const struct clk_hw *[]) {
925-
&clk_div[VC3_DIV1].hw,
926-
&clk_div[VC3_DIV3].hw
924+
&clk_div[VC3_DIV5].hw,
925+
&clk_div[VC3_DIV4].hw
927926
},
928927
.num_parents = 2,
929928
.flags = CLK_SET_RATE_PARENT
@@ -945,33 +944,33 @@ static struct vc3_hw_data clk_mux[] = {
945944
.flags = CLK_SET_RATE_PARENT
946945
}
947946
},
948-
[VC3_SE2_MUX] = {
947+
[VC3_DIFF1_MUX] = {
949948
.data = &(struct vc3_clk_data) {
950-
.offs = VC3_SE2_CTRL_REG0,
951-
.bitmsk = VC3_SE2_CTRL_REG0_SE2_CLK_SEL
949+
.offs = VC3_DIFF1_CTRL_REG,
950+
.bitmsk = VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL
952951
},
953952
.hw.init = &(struct clk_init_data){
954-
.name = "se2_mux",
953+
.name = "diff1_mux",
955954
.ops = &vc3_clk_mux_ops,
956955
.parent_hws = (const struct clk_hw *[]) {
957-
&clk_div[VC3_DIV5].hw,
958-
&clk_div[VC3_DIV4].hw
956+
&clk_div[VC3_DIV1].hw,
957+
&clk_div[VC3_DIV3].hw
959958
},
960959
.num_parents = 2,
961960
.flags = CLK_SET_RATE_PARENT
962961
}
963962
},
964-
[VC3_SE1_MUX] = {
963+
[VC3_DIFF2_MUX] = {
965964
.data = &(struct vc3_clk_data) {
966-
.offs = VC3_SE1_DIV4_CTRL,
967-
.bitmsk = VC3_SE1_DIV4_CTRL_SE1_CLK_SEL
965+
.offs = VC3_DIFF2_CTRL_REG,
966+
.bitmsk = VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL
968967
},
969968
.hw.init = &(struct clk_init_data){
970-
.name = "se1_mux",
969+
.name = "diff2_mux",
971970
.ops = &vc3_clk_mux_ops,
972971
.parent_hws = (const struct clk_hw *[]) {
973-
&clk_div[VC3_DIV5].hw,
974-
&clk_div[VC3_DIV4].hw
972+
&clk_div[VC3_DIV1].hw,
973+
&clk_div[VC3_DIV3].hw
975974
},
976975
.num_parents = 2,
977976
.flags = CLK_SET_RATE_PARENT
@@ -1110,7 +1109,7 @@ static int vc3_probe(struct i2c_client *client)
11101109
name, 0, CLK_SET_RATE_PARENT, 1, 1);
11111110
else
11121111
clk_out[i] = devm_clk_hw_register_fixed_factor_parent_hw(dev,
1113-
name, &clk_mux[i].hw, CLK_SET_RATE_PARENT, 1, 1);
1112+
name, &clk_mux[i - 1].hw, CLK_SET_RATE_PARENT, 1, 1);
11141113

11151114
if (IS_ERR(clk_out[i]))
11161115
return PTR_ERR(clk_out[i]);

‎drivers/clk/sprd/ums512-clk.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -800,7 +800,7 @@ static SPRD_MUX_CLK_DATA(uart1_clk, "uart1-clk", uart_parents,
800800
0x250, 0, 3, UMS512_MUX_FLAG);
801801

802802
static const struct clk_parent_data thm_parents[] = {
803-
{ .fw_name = "ext-32m" },
803+
{ .fw_name = "ext-32k" },
804804
{ .hw = &clk_250k.hw },
805805
};
806806
static SPRD_MUX_CLK_DATA(thm0_clk, "thm0-clk", thm_parents,

‎drivers/clk/tegra/clk-bpmp.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -159,7 +159,7 @@ static unsigned long tegra_bpmp_clk_recalc_rate(struct clk_hw *hw,
159159

160160
err = tegra_bpmp_clk_transfer(clk->bpmp, &msg);
161161
if (err < 0)
162-
return err;
162+
return 0;
163163

164164
return response.rate;
165165
}

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