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perf vendor events intel: Update alderlake/alderlake events to v1.23
Update alderlake and alderlaken events from v1.21 to v1.23 adding the changes from: intel/perfmon@8df4db9 intel/perfmon@846bd24 The tsx_cycles_per_elision metric is updated from PR: intel/perfmon#116 Signed-off-by: Ian Rogers <irogers@google.com> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Edward Baker <edward.baker@intel.com> Cc: Zhengjun Xing <zhengjun.xing@linux.intel.com> Link: https://lore.kernel.org/r/20231026003149.3287633-1-irogers@google.com Signed-off-by: Namhyung Kim <namhyung@kernel.org>
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9 files changed

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‎tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json

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@@ -99,7 +99,7 @@
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},
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{
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"BriefDescription": "Number of cycles within a transaction divided by the number of elisions.",
102-
"MetricExpr": "(cycles\\-t / el\\-start if has_event(cycles\\-t) else 0)",
102+
"MetricExpr": "(cycles\\-t / el\\-start if has_event(el\\-start) else 0)",
103103
"MetricGroup": "transaction",
104104
"MetricName": "tsx_cycles_per_elision",
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"ScaleUnit": "1cycles / elision"

‎tools/perf/pmu-events/arch/x86/alderlake/frontend.json

Lines changed: 36 additions & 6 deletions
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@@ -394,31 +394,61 @@
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled",
397+
"BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE]",
398+
"EventCode": "0x9c",
399+
"EventName": "IDQ_BUBBLES.CORE",
400+
"PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE]",
401+
"SampleAfterValue": "1000003",
402+
"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
406+
"BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]",
407+
"CounterMask": "6",
408+
"EventCode": "0x9c",
409+
"EventName": "IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE",
410+
"PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]",
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"SampleAfterValue": "1000003",
412+
"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]",
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"CounterMask": "1",
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"EventCode": "0x9c",
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"EventName": "IDQ_BUBBLES.CYCLES_FE_WAS_OK",
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"Invert": "1",
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"PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]",
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"SampleAfterValue": "1000003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CORE]",
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"EventCode": "0x9c",
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"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
400-
"PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
430+
"PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CORE]",
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"SampleAfterValue": "1000003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
406-
"BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled",
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"BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE]",
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"CounterMask": "6",
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"EventCode": "0x9c",
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"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
410-
"PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
440+
"PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE]",
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"SampleAfterValue": "1000003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
416-
"BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled",
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"BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK]",
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"CounterMask": "1",
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"EventCode": "0x9c",
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"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
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"Invert": "1",
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"PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
451+
"PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK]",
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"SampleAfterValue": "1000003",
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"UMask": "0x1",
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"Unit": "cpu_core"

‎tools/perf/pmu-events/arch/x86/alderlake/memory.json

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@@ -248,7 +248,7 @@
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
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"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]",
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"EventCode": "0xB7",
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"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
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"MSRIndex": "0x1a6,0x1a7",
@@ -278,7 +278,7 @@
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
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"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]",
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"EventCode": "0xB7",
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"EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
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"MSRIndex": "0x1a6,0x1a7",

‎tools/perf/pmu-events/arch/x86/alderlake/pipeline.json

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@@ -238,6 +238,15 @@
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"UMask": "0x8",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts the number of near taken branch instructions retired.",
243+
"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
245+
"PEBS": "1",
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"SampleAfterValue": "200003",
247+
"UMask": "0xc0",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Taken branch instructions retired.",
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"EventCode": "0xc4",
@@ -411,6 +420,15 @@
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"UMask": "0x7e",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of mispredicted near taken branch instructions retired.",
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"EventCode": "0xc5",
426+
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
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"PEBS": "1",
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"SampleAfterValue": "200003",
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"UMask": "0x80",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
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"EventCode": "0xc5",
@@ -842,7 +860,7 @@
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"Unit": "cpu_core"
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},
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{
845-
"BriefDescription": "INT_MISC.UNKNOWN_BRANCH_CYCLES",
863+
"BriefDescription": "Bubble cycles of BAClear (Unknown Branch).",
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"EventCode": "0xad",
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"EventName": "INT_MISC.UNKNOWN_BRANCH_CYCLES",
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"MSRIndex": "0x3F7",

‎tools/perf/pmu-events/arch/x86/alderlake/uncore-interconnect.json

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@@ -25,6 +25,7 @@
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},
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{
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"BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_REQ_TRK_REQUEST.DRD",
28+
"Deprecated": "1",
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"EventCode": "0x81",
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"EventName": "UNC_ARB_DAT_REQUESTS.RD",
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"PerPkg": "1",
@@ -33,6 +34,7 @@
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},
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{
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"BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_OCCUPANCY.ALL",
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"Deprecated": "1",
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"EventCode": "0x85",
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"EventName": "UNC_ARB_IFA_OCCUPANCY.ALL",
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"PerPkg": "1",

‎tools/perf/pmu-events/arch/x86/alderlaken/memory.json

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@@ -59,7 +59,7 @@
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
62+
"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]",
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"EventCode": "0xB7",
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"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
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"MSRIndex": "0x1a6,0x1a7",
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"UMask": "0x1"
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},
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{
80-
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
80+
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]",
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"EventCode": "0xB7",
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"EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
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"MSRIndex": "0x1a6,0x1a7",

‎tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json

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"SampleAfterValue": "200003",
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"UMask": "0xf7"
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},
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{
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"BriefDescription": "Counts the number of near taken branch instructions retired.",
95+
"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
97+
"PEBS": "1",
98+
"SampleAfterValue": "200003",
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"UMask": "0xc0"
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},
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{
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"BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT",
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"Deprecated": "1",
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"SampleAfterValue": "200003",
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"UMask": "0x7e"
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},
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{
195+
"BriefDescription": "Counts the number of mispredicted near taken branch instructions retired.",
196+
"EventCode": "0xc5",
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"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
198+
"PEBS": "1",
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"SampleAfterValue": "200003",
200+
"UMask": "0x80"
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},
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{
187203
"BriefDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT",
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"Deprecated": "1",

‎tools/perf/pmu-events/arch/x86/alderlaken/uncore-interconnect.json

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"UMask": "0x1",
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"Unit": "ARB"
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},
10+
{
11+
"BriefDescription": "Each cycle counts number of any coherent request at memory controller that were issued by any core.",
12+
"EventCode": "0x85",
13+
"EventName": "UNC_ARB_DAT_OCCUPANCY.ALL",
14+
"PerPkg": "1",
15+
"UMask": "0x1",
16+
"Unit": "ARB"
17+
},
18+
{
19+
"BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core.",
20+
"EventCode": "0x85",
21+
"EventName": "UNC_ARB_DAT_OCCUPANCY.RD",
22+
"PerPkg": "1",
23+
"UMask": "0x2",
24+
"Unit": "ARB"
25+
},
26+
{
27+
"BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_REQ_TRK_REQUEST.DRD",
28+
"Deprecated": "1",
29+
"EventCode": "0x81",
30+
"EventName": "UNC_ARB_DAT_REQUESTS.RD",
31+
"PerPkg": "1",
32+
"UMask": "0x2",
33+
"Unit": "ARB"
34+
},
35+
{
36+
"BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_OCCUPANCY.ALL",
37+
"Deprecated": "1",
38+
"EventCode": "0x85",
39+
"EventName": "UNC_ARB_IFA_OCCUPANCY.ALL",
40+
"PerPkg": "1",
41+
"UMask": "0x1",
42+
"Unit": "ARB"
43+
},
44+
{
45+
"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_OCCUPANCY.RD]",
46+
"EventCode": "0x80",
47+
"EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD",
48+
"PerPkg": "1",
49+
"UMask": "0x2",
50+
"Unit": "ARB"
51+
},
52+
{
53+
"BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_REQUESTS.RD]",
54+
"EventCode": "0x81",
55+
"EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD",
56+
"PerPkg": "1",
57+
"UMask": "0x2",
58+
"Unit": "ARB"
59+
},
1060
{
1161
"BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.",
1262
"EventCode": "0x80",
@@ -15,12 +65,28 @@
1565
"UMask": "0x1",
1666
"Unit": "ARB"
1767
},
68+
{
69+
"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_OCCUPANCY.DRD]",
70+
"EventCode": "0x80",
71+
"EventName": "UNC_ARB_TRK_OCCUPANCY.RD",
72+
"PerPkg": "1",
73+
"UMask": "0x2",
74+
"Unit": "ARB"
75+
},
1876
{
1977
"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
2078
"EventCode": "0x81",
2179
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
2280
"PerPkg": "1",
2381
"UMask": "0x1",
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"Unit": "ARB"
83+
},
84+
{
85+
"BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_REQUEST.DRD]",
86+
"EventCode": "0x81",
87+
"EventName": "UNC_ARB_TRK_REQUESTS.RD",
88+
"PerPkg": "1",
89+
"UMask": "0x2",
90+
"Unit": "ARB"
2591
}
2692
]

‎tools/perf/pmu-events/arch/x86/mapfile.csv

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11
Family-model,Version,Filename,EventType
2-
GenuineIntel-6-(97|9A|B7|BA|BF),v1.21,alderlake,core
3-
GenuineIntel-6-BE,v1.21,alderlaken,core
2+
GenuineIntel-6-(97|9A|B7|BA|BF),v1.23,alderlake,core
3+
GenuineIntel-6-BE,v1.23,alderlaken,core
44
GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core
55
GenuineIntel-6-(3D|47),v28,broadwell,core
66
GenuineIntel-6-56,v11,broadwellde,core

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