@@ -66,6 +66,18 @@ static void tqmx86_gpio_write(struct tqmx86_gpio_data *gd, u8 val,
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iowrite8 (val , gd -> io_base + reg );
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}
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+ static void tqmx86_gpio_clrsetbits (struct tqmx86_gpio_data * gpio ,
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+ u8 clr , u8 set , unsigned int reg )
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+ __must_hold (& gpio - > spinlock )
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+ {
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+ u8 val = tqmx86_gpio_read (gpio , reg );
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+
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+ val &= ~clr ;
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+ val |= set ;
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+
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+ tqmx86_gpio_write (gpio , val , reg );
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+ }
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+
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static int tqmx86_gpio_get (struct gpio_chip * chip , unsigned int offset )
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{
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struct tqmx86_gpio_data * gpio = gpiochip_get_data (chip );
@@ -118,7 +130,7 @@ static int tqmx86_gpio_get_direction(struct gpio_chip *chip,
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static void tqmx86_gpio_irq_config (struct tqmx86_gpio_data * gpio , int hwirq )
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__must_hold (& gpio - > spinlock )
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{
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- u8 type = TQMX86_INT_TRIG_NONE , gpiic ;
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+ u8 type = TQMX86_INT_TRIG_NONE ;
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int gpiic_irq = hwirq - TQMX86_NGPO ;
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if (gpio -> irq_type [hwirq ] & TQMX86_INT_UNMASKED ) {
@@ -130,10 +142,10 @@ static void tqmx86_gpio_irq_config(struct tqmx86_gpio_data *gpio, int hwirq)
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: TQMX86_INT_TRIG_RISING ;
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}
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- gpiic = tqmx86_gpio_read (gpio , TQMX86_GPIIC );
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- gpiic &= ~ TQMX86_GPIIC_MASK (gpiic_irq );
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- gpiic |= TQMX86_GPIIC_CONFIG (gpiic_irq , type );
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- tqmx86_gpio_write ( gpio , gpiic , TQMX86_GPIIC );
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+ tqmx86_gpio_clrsetbits (gpio ,
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+ TQMX86_GPIIC_MASK (gpiic_irq ),
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+ TQMX86_GPIIC_CONFIG (gpiic_irq , type ),
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+ TQMX86_GPIIC );
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}
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static void tqmx86_gpio_irq_mask (struct irq_data * data )
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