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Naveen Mamindlapallidavem330
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octeontx2-af: Always configure NIX TX link credits based on max frame size
Currently the NIX TX link credits are initialized based on the max frame size that can be transmitted on a link but when the MTU is changed, the NIX TX link credits are reprogrammed by the SW based on the new MTU value. Since SMQ max packet length is programmed to max frame size by default, there is a chance that NIX TX may stall while sending a max frame sized packet on the link with insufficient credits to send the packet all at once. This patch avoids stall issue by not changing the link credits dynamically when the MTU is changed. Fixes: 1c74b89 ("octeontx2-af: Wait for TX link idle for credits change") Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com> Signed-off-by: Nithin Kumar Dabilpuram <ndabilpuram@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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  • drivers/net/ethernet/marvell/octeontx2/af

1 file changed

+3
-107
lines changed

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

Lines changed: 3 additions & 107 deletions
Original file line numberDiff line numberDiff line change
@@ -4143,90 +4143,18 @@ static void nix_find_link_frs(struct rvu *rvu,
41434143
req->minlen = minlen;
41444144
}
41454145

4146-
static int
4147-
nix_config_link_credits(struct rvu *rvu, int blkaddr, int link,
4148-
u16 pcifunc, u64 tx_credits)
4149-
{
4150-
struct rvu_hwinfo *hw = rvu->hw;
4151-
int pf = rvu_get_pf(pcifunc);
4152-
u8 cgx_id = 0, lmac_id = 0;
4153-
unsigned long poll_tmo;
4154-
bool restore_tx_en = 0;
4155-
struct nix_hw *nix_hw;
4156-
u64 cfg, sw_xoff = 0;
4157-
u32 schq = 0;
4158-
u32 credits;
4159-
int rc;
4160-
4161-
nix_hw = get_nix_hw(rvu->hw, blkaddr);
4162-
if (!nix_hw)
4163-
return NIX_AF_ERR_INVALID_NIXBLK;
4164-
4165-
if (tx_credits == nix_hw->tx_credits[link])
4166-
return 0;
4167-
4168-
/* Enable cgx tx if disabled for credits to be back */
4169-
if (is_pf_cgxmapped(rvu, pf)) {
4170-
rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
4171-
restore_tx_en = !rvu_cgx_config_tx(rvu_cgx_pdata(cgx_id, rvu),
4172-
lmac_id, true);
4173-
}
4174-
4175-
mutex_lock(&rvu->rsrc_lock);
4176-
/* Disable new traffic to link */
4177-
if (hw->cap.nix_shaping) {
4178-
schq = nix_get_tx_link(rvu, pcifunc);
4179-
sw_xoff = rvu_read64(rvu, blkaddr, NIX_AF_TL1X_SW_XOFF(schq));
4180-
rvu_write64(rvu, blkaddr,
4181-
NIX_AF_TL1X_SW_XOFF(schq), BIT_ULL(0));
4182-
}
4183-
4184-
rc = NIX_AF_ERR_LINK_CREDITS;
4185-
poll_tmo = jiffies + usecs_to_jiffies(200000);
4186-
/* Wait for credits to return */
4187-
do {
4188-
if (time_after(jiffies, poll_tmo))
4189-
goto exit;
4190-
usleep_range(100, 200);
4191-
4192-
cfg = rvu_read64(rvu, blkaddr,
4193-
NIX_AF_TX_LINKX_NORM_CREDIT(link));
4194-
credits = (cfg >> 12) & 0xFFFFFULL;
4195-
} while (credits != nix_hw->tx_credits[link]);
4196-
4197-
cfg &= ~(0xFFFFFULL << 12);
4198-
cfg |= (tx_credits << 12);
4199-
rvu_write64(rvu, blkaddr, NIX_AF_TX_LINKX_NORM_CREDIT(link), cfg);
4200-
rc = 0;
4201-
4202-
nix_hw->tx_credits[link] = tx_credits;
4203-
4204-
exit:
4205-
/* Enable traffic back */
4206-
if (hw->cap.nix_shaping && !sw_xoff)
4207-
rvu_write64(rvu, blkaddr, NIX_AF_TL1X_SW_XOFF(schq), 0);
4208-
4209-
/* Restore state of cgx tx */
4210-
if (restore_tx_en)
4211-
rvu_cgx_config_tx(rvu_cgx_pdata(cgx_id, rvu), lmac_id, false);
4212-
4213-
mutex_unlock(&rvu->rsrc_lock);
4214-
return rc;
4215-
}
4216-
42174146
int rvu_mbox_handler_nix_set_hw_frs(struct rvu *rvu, struct nix_frs_cfg *req,
42184147
struct msg_rsp *rsp)
42194148
{
42204149
struct rvu_hwinfo *hw = rvu->hw;
42214150
u16 pcifunc = req->hdr.pcifunc;
42224151
int pf = rvu_get_pf(pcifunc);
4223-
int blkaddr, schq, link = -1;
4224-
struct nix_txsch *txsch;
4225-
u64 cfg, lmac_fifo_len;
4152+
int blkaddr, link = -1;
42264153
struct nix_hw *nix_hw;
42274154
struct rvu_pfvf *pfvf;
42284155
u8 cgx = 0, lmac = 0;
42294156
u16 max_mtu;
4157+
u64 cfg;
42304158

42314159
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
42324160
if (blkaddr < 0)
@@ -4247,25 +4175,6 @@ int rvu_mbox_handler_nix_set_hw_frs(struct rvu *rvu, struct nix_frs_cfg *req,
42474175
if (req->update_minlen && req->minlen < NIC_HW_MIN_FRS)
42484176
return NIX_AF_ERR_FRS_INVALID;
42494177

4250-
/* Check if requester wants to update SMQ's */
4251-
if (!req->update_smq)
4252-
goto rx_frscfg;
4253-
4254-
/* Update min/maxlen in each of the SMQ attached to this PF/VF */
4255-
txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ];
4256-
mutex_lock(&rvu->rsrc_lock);
4257-
for (schq = 0; schq < txsch->schq.max; schq++) {
4258-
if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc)
4259-
continue;
4260-
cfg = rvu_read64(rvu, blkaddr, NIX_AF_SMQX_CFG(schq));
4261-
cfg = (cfg & ~(0xFFFFULL << 8)) | ((u64)req->maxlen << 8);
4262-
if (req->update_minlen)
4263-
cfg = (cfg & ~0x7FULL) | ((u64)req->minlen & 0x7F);
4264-
rvu_write64(rvu, blkaddr, NIX_AF_SMQX_CFG(schq), cfg);
4265-
}
4266-
mutex_unlock(&rvu->rsrc_lock);
4267-
4268-
rx_frscfg:
42694178
/* Check if config is for SDP link */
42704179
if (req->sdp_link) {
42714180
if (!hw->sdp_links)
@@ -4288,7 +4197,6 @@ int rvu_mbox_handler_nix_set_hw_frs(struct rvu *rvu, struct nix_frs_cfg *req,
42884197
if (link < 0)
42894198
return NIX_AF_ERR_RX_LINK_INVALID;
42904199

4291-
42924200
linkcfg:
42934201
nix_find_link_frs(rvu, req, pcifunc);
42944202

@@ -4298,19 +4206,7 @@ int rvu_mbox_handler_nix_set_hw_frs(struct rvu *rvu, struct nix_frs_cfg *req,
42984206
cfg = (cfg & ~0xFFFFULL) | req->minlen;
42994207
rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link), cfg);
43004208

4301-
if (req->sdp_link || pf == 0)
4302-
return 0;
4303-
4304-
/* Update transmit credits for CGX links */
4305-
lmac_fifo_len = rvu_cgx_get_lmac_fifolen(rvu, cgx, lmac);
4306-
if (!lmac_fifo_len) {
4307-
dev_err(rvu->dev,
4308-
"%s: Failed to get CGX/RPM%d:LMAC%d FIFO size\n",
4309-
__func__, cgx, lmac);
4310-
return 0;
4311-
}
4312-
return nix_config_link_credits(rvu, blkaddr, link, pcifunc,
4313-
(lmac_fifo_len - req->maxlen) / 16);
4209+
return 0;
43144210
}
43154211

43164212
int rvu_mbox_handler_nix_set_rx_cfg(struct rvu *rvu, struct nix_rx_cfg *req,

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