Skip to content

Commit 9f17728

Browse files
xpardee-createjwrdegoede
xpardee-create
authored and
jwrdegoede
committed
platform/x86:intel/pmc: Add Meteor Lake IOE-P PMC related maps
Add device ID and register maps for the PMC in IO expansion die P in Meteor Lake. Signed-off-by: Xi Pardee <xi.pardee@intel.com> Signed-off-by: Rajvi Jingar <rajvi.jingar@linux.intel.com> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Link: https://lore.kernel.org/r/20230613225347.2720665-8-rajvi.jingar@linux.intel.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
1 parent 23e74e3 commit 9f17728

File tree

2 files changed

+343
-0
lines changed

2 files changed

+343
-0
lines changed

‎drivers/platform/x86/intel/pmc/core.h

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -252,12 +252,15 @@ enum ppfear_regs {
252252
#define MTL_LPM_LIVE_STATUS_OFFSET 0x175C
253253
#define MTL_PMC_LTR_IOE_PMC 0x1C0C
254254
#define MTL_PMC_LTR_ESE 0x1BAC
255+
#define MTL_PMC_LTR_RESERVED 0x1BA4
256+
#define MTL_IOE_PMC_MMIO_REG_LEN 0x23A4
255257
#define MTL_SOCM_NUM_IP_IGN_ALLOWED 25
256258
#define MTL_SOC_PMC_MMIO_REG_LEN 0x2708
257259
#define MTL_PMC_LTR_SPG 0x1B74
258260

259261
/* Meteor Lake PGD PFET Enable Ack Status */
260262
#define MTL_SOCM_PPFEAR_NUM_ENTRIES 8
263+
#define MTL_IOE_PPFEAR_NUM_ENTRIES 10
261264

262265
extern const char *pmc_lpm_modes[];
263266

@@ -457,6 +460,24 @@ extern const struct pmc_bit_map mtl_socm_vnn_misc_status_map[];
457460
extern const struct pmc_bit_map mtl_socm_signal_status_map[];
458461
extern const struct pmc_bit_map *mtl_socm_lpm_maps[];
459462
extern const struct pmc_reg_map mtl_socm_reg_map;
463+
extern const struct pmc_bit_map mtl_ioep_pfear_map[];
464+
extern const struct pmc_bit_map *ext_mtl_ioep_pfear_map[];
465+
extern const struct pmc_bit_map mtl_ioep_ltr_show_map[];
466+
extern const struct pmc_bit_map mtl_ioep_clocksource_status_map[];
467+
extern const struct pmc_bit_map mtl_ioep_power_gating_status_0_map[];
468+
extern const struct pmc_bit_map mtl_ioep_power_gating_status_1_map[];
469+
extern const struct pmc_bit_map mtl_ioep_power_gating_status_2_map[];
470+
extern const struct pmc_bit_map mtl_ioep_d3_status_0_map[];
471+
extern const struct pmc_bit_map mtl_ioep_d3_status_1_map[];
472+
extern const struct pmc_bit_map mtl_ioep_d3_status_2_map[];
473+
extern const struct pmc_bit_map mtl_ioep_d3_status_3_map[];
474+
extern const struct pmc_bit_map mtl_ioep_vnn_req_status_0_map[];
475+
extern const struct pmc_bit_map mtl_ioep_vnn_req_status_1_map[];
476+
extern const struct pmc_bit_map mtl_ioep_vnn_req_status_2_map[];
477+
extern const struct pmc_bit_map mtl_ioep_vnn_req_status_3_map[];
478+
extern const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[];
479+
extern const struct pmc_bit_map *mtl_ioep_lpm_maps[];
480+
extern const struct pmc_reg_map mtl_ioep_reg_map;
460481

461482
extern void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev);
462483
extern int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value);

‎drivers/platform/x86/intel/pmc/mtl.c

Lines changed: 322 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -467,12 +467,334 @@ const struct pmc_reg_map mtl_socm_reg_map = {
467467
.lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
468468
};
469469

470+
const struct pmc_bit_map mtl_ioep_pfear_map[] = {
471+
{"PMC_0", BIT(0)},
472+
{"OPI", BIT(1)},
473+
{"TCSS", BIT(2)},
474+
{"RSVD3", BIT(3)},
475+
{"SPA", BIT(4)},
476+
{"SPB", BIT(5)},
477+
{"SPC", BIT(6)},
478+
{"IOE_D2D_3", BIT(7)},
479+
480+
{"RSVD8", BIT(0)},
481+
{"RSVD9", BIT(1)},
482+
{"SPE", BIT(2)},
483+
{"RSVD11", BIT(3)},
484+
{"RSVD12", BIT(4)},
485+
{"SPD", BIT(5)},
486+
{"ACE_7", BIT(6)},
487+
{"RSVD15", BIT(7)},
488+
489+
{"ACE_0", BIT(0)},
490+
{"FIACPCB_P", BIT(1)},
491+
{"P2S", BIT(2)},
492+
{"RSVD19", BIT(3)},
493+
{"ACE_8", BIT(4)},
494+
{"IOE_D2D_0", BIT(5)},
495+
{"FUSE", BIT(6)},
496+
{"RSVD23", BIT(7)},
497+
498+
{"FIACPCB_P5", BIT(0)},
499+
{"ACE_3", BIT(1)},
500+
{"RSF5", BIT(2)},
501+
{"ACE_2", BIT(3)},
502+
{"ACE_4", BIT(4)},
503+
{"RSVD29", BIT(5)},
504+
{"RSF10", BIT(6)},
505+
{"MPFPW5", BIT(7)},
506+
507+
{"PSF9", BIT(0)},
508+
{"MPFPW4", BIT(1)},
509+
{"RSVD34", BIT(2)},
510+
{"RSVD35", BIT(3)},
511+
{"RSVD36", BIT(4)},
512+
{"RSVD37", BIT(5)},
513+
{"RSVD38", BIT(6)},
514+
{"RSVD39", BIT(7)},
515+
516+
{"SBR0", BIT(0)},
517+
{"SBR1", BIT(1)},
518+
{"SBR2", BIT(2)},
519+
{"SBR3", BIT(3)},
520+
{"SBR4", BIT(4)},
521+
{"SBR5", BIT(5)},
522+
{"RSVD46", BIT(6)},
523+
{"RSVD47", BIT(7)},
524+
525+
{"RSVD48", BIT(0)},
526+
{"FIA_P5", BIT(1)},
527+
{"RSVD50", BIT(2)},
528+
{"RSVD51", BIT(3)},
529+
{"RSVD52", BIT(4)},
530+
{"RSVD53", BIT(5)},
531+
{"RSVD54", BIT(6)},
532+
{"ACE_1", BIT(7)},
533+
534+
{"RSVD56", BIT(0)},
535+
{"ACE_5", BIT(1)},
536+
{"RSVD58", BIT(2)},
537+
{"G5FPW1", BIT(3)},
538+
{"RSVD60", BIT(4)},
539+
{"ACE_6", BIT(5)},
540+
{"RSVD62", BIT(6)},
541+
{"GBETSN1", BIT(7)},
542+
543+
{"RSVD64", BIT(0)},
544+
{"FIA", BIT(1)},
545+
{"RSVD66", BIT(2)},
546+
{"FIA_P", BIT(3)},
547+
{"TAM", BIT(4)},
548+
{"GBETSN", BIT(5)},
549+
{"IOE_D2D_2", BIT(6)},
550+
{"IOE_D2D_1", BIT(7)},
551+
552+
{"SPF", BIT(0)},
553+
{"PMC_1", BIT(1)},
554+
{}
555+
};
556+
557+
const struct pmc_bit_map *ext_mtl_ioep_pfear_map[] = {
558+
mtl_ioep_pfear_map,
559+
NULL
560+
};
561+
562+
const struct pmc_bit_map mtl_ioep_ltr_show_map[] = {
563+
{"SOUTHPORT_A", CNP_PMC_LTR_SPA},
564+
{"SOUTHPORT_B", CNP_PMC_LTR_SPB},
565+
{"SATA", CNP_PMC_LTR_SATA},
566+
{"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
567+
{"XHCI", CNP_PMC_LTR_XHCI},
568+
{"SOUTHPORT_F", ADL_PMC_LTR_SPF},
569+
{"ME", CNP_PMC_LTR_ME},
570+
{"SATA1", CNP_PMC_LTR_EVA},
571+
{"SOUTHPORT_C", CNP_PMC_LTR_SPC},
572+
{"HD_AUDIO", CNP_PMC_LTR_AZ},
573+
{"CNV", CNP_PMC_LTR_CNV},
574+
{"LPSS", CNP_PMC_LTR_LPSS},
575+
{"SOUTHPORT_D", CNP_PMC_LTR_SPD},
576+
{"SOUTHPORT_E", CNP_PMC_LTR_SPE},
577+
{"SATA2", CNP_PMC_LTR_CAM},
578+
{"ESPI", CNP_PMC_LTR_ESPI},
579+
{"SCC", CNP_PMC_LTR_SCC},
580+
{"Reserved", MTL_PMC_LTR_RESERVED},
581+
{"UFSX2", CNP_PMC_LTR_UFSX2},
582+
{"EMMC", CNP_PMC_LTR_EMMC},
583+
{"WIGIG", ICL_PMC_LTR_WIGIG},
584+
{"THC0", TGL_PMC_LTR_THC0},
585+
{"THC1", TGL_PMC_LTR_THC1},
586+
{"SOUTHPORT_G", MTL_PMC_LTR_SPG},
587+
588+
/* Below two cannot be used for LTR_IGNORE */
589+
{"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
590+
{"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
591+
{}
592+
};
593+
594+
const struct pmc_bit_map mtl_ioep_clocksource_status_map[] = {
595+
{"AON2_OFF_STS", BIT(0)},
596+
{"AON3_OFF_STS", BIT(1)},
597+
{"AON4_OFF_STS", BIT(2)},
598+
{"AON5_OFF_STS", BIT(3)},
599+
{"AON1_OFF_STS", BIT(4)},
600+
{"TBT_PLL_OFF_STS", BIT(5)},
601+
{"TMU_PLL_OFF_STS", BIT(6)},
602+
{"BCLK_PLL_OFF_STS", BIT(7)},
603+
{"D2D_PLL_OFF_STS", BIT(8)},
604+
{"AON3_SPL_OFF_STS", BIT(9)},
605+
{"MPFPW4_0_PLL_OFF_STS", BIT(12)},
606+
{"MPFPW5_0_PLL_OFF_STS", BIT(13)},
607+
{"G5FPW_0_PLL_OFF_STS", BIT(14)},
608+
{"G5FPW_1_PLL_OFF_STS", BIT(15)},
609+
{"XTAL_AGGR_OFF_STS", BIT(17)},
610+
{"FABRIC_PLL_OFF_STS", BIT(25)},
611+
{"SOC_PLL_OFF_STS", BIT(26)},
612+
{"REF_PLL_OFF_STS", BIT(28)},
613+
{"RTC_PLL_OFF_STS", BIT(31)},
614+
{}
615+
};
616+
617+
const struct pmc_bit_map mtl_ioep_power_gating_status_0_map[] = {
618+
{"PMC_PGD0_PG_STS", BIT(0)},
619+
{"DMI_PGD0_PG_STS", BIT(1)},
620+
{"TCSS_PGD0_PG_STS", BIT(2)},
621+
{"SPA_PGD0_PG_STS", BIT(4)},
622+
{"SPB_PGD0_PG_STS", BIT(5)},
623+
{"SPC_PGD0_PG_STS", BIT(6)},
624+
{"IOE_D2D_PGD3_PG_STS", BIT(7)},
625+
{"SPE_PGD0_PG_STS", BIT(10)},
626+
{"SPD_PGD0_PG_STS", BIT(13)},
627+
{"ACE_PGD7_PG_STS", BIT(14)},
628+
{"ACE_PGD0_PG_STS", BIT(16)},
629+
{"FIACPCB_P_PGD0_PG_STS", BIT(17)},
630+
{"P2S_PGD0_PG_STS", BIT(18)},
631+
{"ACE_PGD8_PG_STS", BIT(20)},
632+
{"IOE_D2D_PGD0_PG_STS", BIT(21)},
633+
{"FUSE_PGD0_PG_STS", BIT(22)},
634+
{"FIACPCB_P5_PGD0_PG_STS", BIT(24)},
635+
{"ACE_PGD3_PG_STS", BIT(25)},
636+
{"PSF5_PGD0_PG_STS", BIT(26)},
637+
{"ACE_PGD2_PG_STS", BIT(27)},
638+
{"ACE_PGD4_PG_STS", BIT(28)},
639+
{"PSF10_PGD0_PG_STS", BIT(30)},
640+
{"MPFPW5_PGD0_PG_STS", BIT(31)},
641+
{}
642+
};
643+
644+
const struct pmc_bit_map mtl_ioep_power_gating_status_1_map[] = {
645+
{"PSF9_PGD0_PG_STS", BIT(0)},
646+
{"MPFPW4_PGD0_PG_STS", BIT(1)},
647+
{"SBR0_PGD0_PG_STS", BIT(8)},
648+
{"SBR1_PGD0_PG_STS", BIT(9)},
649+
{"SBR2_PGD0_PG_STS", BIT(10)},
650+
{"SBR3_PGD0_PG_STS", BIT(11)},
651+
{"SBR4_PGD0_PG_STS", BIT(12)},
652+
{"SBR5_PGD0_PG_STS", BIT(13)},
653+
{"FIA_P5_PGD0_PG_STS", BIT(17)},
654+
{"ACE_PGD1_PGD0_PG_STS", BIT(23)},
655+
{"ACE_PGD5_PGD1_PG_STS", BIT(25)},
656+
{"G5FPW1_PGD0_PG_STS", BIT(27)},
657+
{"ACE_PGD6_PG_STS", BIT(29)},
658+
{"GBETSN1_PGD0_PG_STS", BIT(31)},
659+
{}
660+
};
661+
662+
const struct pmc_bit_map mtl_ioep_power_gating_status_2_map[] = {
663+
{"FIA_PGD0_PG_STS", BIT(1)},
664+
{"FIA_P_PGD0_PG_STS", BIT(3)},
665+
{"TAM_PGD0_PG_STS", BIT(4)},
666+
{"GBETSN_PGD0_PG_STS", BIT(5)},
667+
{"IOE_D2D_PGD2_PG_STS", BIT(6)},
668+
{"IOE_D2D_PGD1_PG_STS", BIT(7)},
669+
{"SPF_PGD0_PG_STS", BIT(8)},
670+
{"PMC_PGD1_PG_STS", BIT(9)},
671+
{}
672+
};
673+
674+
const struct pmc_bit_map mtl_ioep_d3_status_0_map[] = {
675+
{"SPF_D3_STS", BIT(0)},
676+
{"SPA_D3_STS", BIT(12)},
677+
{"SPB_D3_STS", BIT(13)},
678+
{"SPC_D3_STS", BIT(14)},
679+
{"SPD_D3_STS", BIT(15)},
680+
{"SPE_D3_STS", BIT(16)},
681+
{"DMI_D3_STS", BIT(22)},
682+
{}
683+
};
684+
685+
const struct pmc_bit_map mtl_ioep_d3_status_1_map[] = {
686+
{"GBETSN1_D3_STS", BIT(14)},
687+
{"P2S_D3_STS", BIT(24)},
688+
{}
689+
};
690+
691+
const struct pmc_bit_map mtl_ioep_d3_status_2_map[] = {
692+
{}
693+
};
694+
695+
const struct pmc_bit_map mtl_ioep_d3_status_3_map[] = {
696+
{"GBETSN_D3_STS", BIT(13)},
697+
{"ACE_D3_STS", BIT(23)},
698+
{}
699+
};
700+
701+
const struct pmc_bit_map mtl_ioep_vnn_req_status_0_map[] = {
702+
{"FIA_VNN_REQ_STS", BIT(17)},
703+
{}
704+
};
705+
706+
const struct pmc_bit_map mtl_ioep_vnn_req_status_1_map[] = {
707+
{"DFXAGG_VNN_REQ_STS", BIT(8)},
708+
{}
709+
};
710+
711+
const struct pmc_bit_map mtl_ioep_vnn_req_status_2_map[] = {
712+
{}
713+
};
714+
715+
const struct pmc_bit_map mtl_ioep_vnn_req_status_3_map[] = {
716+
{"DTS0_VNN_REQ_STS", BIT(7)},
717+
{"DISP_VNN_REQ_STS", BIT(19)},
718+
{}
719+
};
720+
721+
const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[] = {
722+
{"CPU_C10_REQ_STS", BIT(0)},
723+
{"TS_OFF_REQ_STS", BIT(1)},
724+
{"PNDE_MET_REQ_STS", BIT(2)},
725+
{"PCIE_DEEP_PM_REQ_STS", BIT(3)},
726+
{"PMC_CLK_THROTTLE_EN_REQ_STS", BIT(4)},
727+
{"NPK_VNNAON_REQ_STS", BIT(5)},
728+
{"VNN_SOC_REQ_STS", BIT(6)},
729+
{"USB_DEVICE_ATTACHED_REQ_STS", BIT(8)},
730+
{"FIA_EXIT_REQ_STS", BIT(9)},
731+
{"USB2_SUS_PG_REQ_STS", BIT(10)},
732+
{"PLT_GREATER_REQ_STS", BIT(11)},
733+
{"PCIE_CLKREQ_REQ_STS", BIT(12)},
734+
{"PMC_IDLE_FB_OCP_REQ_STS", BIT(13)},
735+
{"PM_SYNC_STATES_REQ_STS", BIT(14)},
736+
{"EA_REQ_STS", BIT(15)},
737+
{"MPHY_CORE_OFF_REQ_STS", BIT(16)},
738+
{"BRK_EV_EN_REQ_STS", BIT(17)},
739+
{"AUTO_DEMO_EN_REQ_STS", BIT(18)},
740+
{"ITSS_CLK_SRC_REQ_STS", BIT(19)},
741+
{"LPC_CLK_SRC_REQ_STS", BIT(20)},
742+
{"ARC_IDLE_REQ_STS", BIT(21)},
743+
{"MPHY_SUS_REQ_STS", BIT(22)},
744+
{"FIA_DEEP_PM_REQ_STS", BIT(23)},
745+
{"UXD_CONNECTED_REQ_STS", BIT(24)},
746+
{"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25)},
747+
{"USB2_VNNAON_ACT_REQ_STS", BIT(26)},
748+
{"PRE_WAKE0_REQ_STS", BIT(27)},
749+
{"PRE_WAKE1_REQ_STS", BIT(28)},
750+
{"PRE_WAKE2_EN_REQ_STS", BIT(29)},
751+
{"WOV_REQ_STS", BIT(30)},
752+
{"CNVI_V1P05_REQ_STS", BIT(31)},
753+
{}
754+
};
755+
756+
const struct pmc_bit_map *mtl_ioep_lpm_maps[] = {
757+
mtl_ioep_clocksource_status_map,
758+
mtl_ioep_power_gating_status_0_map,
759+
mtl_ioep_power_gating_status_1_map,
760+
mtl_ioep_power_gating_status_2_map,
761+
mtl_ioep_d3_status_0_map,
762+
mtl_ioep_d3_status_1_map,
763+
mtl_ioep_d3_status_2_map,
764+
mtl_ioep_d3_status_3_map,
765+
mtl_ioep_vnn_req_status_0_map,
766+
mtl_ioep_vnn_req_status_1_map,
767+
mtl_ioep_vnn_req_status_2_map,
768+
mtl_ioep_vnn_req_status_3_map,
769+
mtl_ioep_vnn_misc_status_map,
770+
mtl_socm_signal_status_map,
771+
NULL
772+
};
773+
774+
const struct pmc_reg_map mtl_ioep_reg_map = {
775+
.regmap_length = MTL_IOE_PMC_MMIO_REG_LEN,
776+
.pfear_sts = ext_mtl_ioep_pfear_map,
777+
.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
778+
.ppfear_buckets = MTL_IOE_PPFEAR_NUM_ENTRIES,
779+
.lpm_status_offset = MTL_LPM_STATUS_OFFSET,
780+
.lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
781+
.lpm_sts = mtl_ioep_lpm_maps,
782+
.ltr_show_sts = mtl_ioep_ltr_show_map,
783+
.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
784+
.ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,
785+
};
786+
470787
#define PMC_DEVID_SOCM 0x7e7f
788+
#define PMC_DEVID_IOEP 0x7ecf
471789
static struct pmc_info mtl_pmc_info_list[] = {
472790
{
473791
.devid = PMC_DEVID_SOCM,
474792
.map = &mtl_socm_reg_map,
475793
},
794+
{
795+
.devid = PMC_DEVID_IOEP,
796+
.map = &mtl_ioep_reg_map,
797+
},
476798
{}
477799
};
478800

0 commit comments

Comments
 (0)