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spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer
While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer. Fixes: 9ac8d17 ("spi: add support for microchip fpga spi controllers") Signed-off-by: Steve Wilkins <steve.wilkins@raymarine.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20240715-flammable-provoke-459226d08e70@wendy Signed-off-by: Mark Brown <broonie@kernel.org>
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drivers/spi/spi-microchip-core.c

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@@ -91,6 +91,8 @@
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#define REG_CONTROL2 (0x28)
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#define REG_COMMAND (0x2c)
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#define COMMAND_CLRFRAMECNT BIT(4)
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#define COMMAND_TXFIFORST BIT(3)
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#define COMMAND_RXFIFORST BIT(2)
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#define REG_PKTSIZE (0x30)
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#define REG_CMD_SIZE (0x34)
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#define REG_HWSTATUS (0x38)
@@ -496,6 +498,8 @@ static int mchp_corespi_transfer_one(struct spi_controller *host,
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mchp_corespi_set_xfer_size(spi, (spi->tx_len > FIFO_DEPTH)
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? FIFO_DEPTH : spi->tx_len);
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mchp_corespi_write(spi, REG_COMMAND, COMMAND_RXFIFORST | COMMAND_TXFIFORST);
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mchp_corespi_write(spi, REG_SLAVE_SELECT, spi->pending_slave_select);
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while (spi->tx_len)

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