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97 | 97 | #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */
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98 | 98 | #define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */
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99 | 99 | #define X86_FEATURE_AMD_LBR_V2 ( 3*32+17) /* AMD Last Branch Record Extension Version 2 */
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100 |
| -#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */ |
| 100 | +/* FREE, was #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) "" LFENCE synchronizes RDTSC */ |
101 | 101 | #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */
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102 | 102 | #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */
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103 | 103 | #define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */
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226 | 226 |
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227 | 227 | /* Virtualization flags: Linux defined, word 8 */
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228 | 228 | #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
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229 |
| -#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ |
230 |
| -#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ |
231 |
| -#define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ |
232 |
| -#define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ |
| 229 | +#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 1) /* Intel FlexPriority */ |
| 230 | +#define X86_FEATURE_EPT ( 8*32+ 2) /* Intel Extended Page Table */ |
| 231 | +#define X86_FEATURE_VPID ( 8*32+ 3) /* Intel Virtual Processor ID */ |
233 | 232 |
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234 | 233 | #define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer VMMCALL to VMCALL */
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235 | 234 | #define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */
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307 | 306 | #define X86_FEATURE_SGX_EDECCSSA (11*32+18) /* "" SGX EDECCSSA user leaf function */
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308 | 307 | #define X86_FEATURE_CALL_DEPTH (11*32+19) /* "" Call depth tracking for RSB stuffing */
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309 | 308 | #define X86_FEATURE_MSR_TSX_CTRL (11*32+20) /* "" MSR IA32_TSX_CTRL (Intel) implemented */
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| 309 | +#define X86_FEATURE_SMBA (11*32+21) /* "" Slow Memory Bandwidth Allocation */ |
| 310 | +#define X86_FEATURE_BMEC (11*32+22) /* "" Bandwidth Monitoring Event Configuration */ |
310 | 311 |
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311 | 312 | /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
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312 | 313 | #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
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313 | 314 | #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
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314 | 315 | #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* "" CMPccXADD instructions */
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| 316 | +#define X86_FEATURE_ARCH_PERFMON_EXT (12*32+ 8) /* "" Intel Architectural PerfMon Extension */ |
| 317 | +#define X86_FEATURE_FZRM (12*32+10) /* "" Fast zero-length REP MOVSB */ |
| 318 | +#define X86_FEATURE_FSRS (12*32+11) /* "" Fast short REP STOSB */ |
| 319 | +#define X86_FEATURE_FSRC (12*32+12) /* "" Fast short REP {CMPSB,SCASB} */ |
315 | 320 | #define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */
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316 | 321 | #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */
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317 | 322 | #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */
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| 323 | +#define X86_FEATURE_LAM (12*32+26) /* Linear Address Masking */ |
318 | 324 |
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319 | 325 | /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
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320 | 326 | #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
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331 | 337 | #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */
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332 | 338 | #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */
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333 | 339 | #define X86_FEATURE_CPPC (13*32+27) /* Collaborative Processor Performance Control */
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| 340 | +#define X86_FEATURE_AMD_PSFD (13*32+28) /* "" Predictive Store Forwarding Disable */ |
334 | 341 | #define X86_FEATURE_BTC_NO (13*32+29) /* "" Not vulnerable to Branch Type Confusion */
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335 | 342 | #define X86_FEATURE_BRS (13*32+31) /* Branch Sampling available */
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336 | 343 |
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363 | 370 | #define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */
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364 | 371 | #define X86_FEATURE_X2AVIC (15*32+18) /* Virtual x2apic */
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365 | 372 | #define X86_FEATURE_V_SPEC_CTRL (15*32+20) /* Virtual SPEC_CTRL */
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| 373 | +#define X86_FEATURE_VNMI (15*32+25) /* Virtual NMI */ |
366 | 374 | #define X86_FEATURE_SVME_ADDR_CHK (15*32+28) /* "" SVME addr check */
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367 | 375 |
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368 | 376 | /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
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427 | 435 | #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* "" Virtual TSC_AUX */
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428 | 436 | #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */
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429 | 437 |
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| 438 | +/* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */ |
| 439 | +#define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* "" No Nested Data Breakpoints */ |
| 440 | +#define X86_FEATURE_LFENCE_RDTSC (20*32+ 2) /* "" LFENCE always serializing / synchronizes RDTSC */ |
| 441 | +#define X86_FEATURE_NULL_SEL_CLR_BASE (20*32+ 6) /* "" Null Selector Clears Base */ |
| 442 | +#define X86_FEATURE_AUTOIBRS (20*32+ 8) /* "" Automatic IBRS */ |
| 443 | +#define X86_FEATURE_NO_SMM_CTL_MSR (20*32+ 9) /* "" SMM_CTL MSR is not present */ |
| 444 | + |
430 | 445 | /*
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431 | 446 | * BUG word(s)
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432 | 447 | */
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467 | 482 | #define X86_BUG_MMIO_UNKNOWN X86_BUG(26) /* CPU is too old and its MMIO Stale Data status is unknown */
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468 | 483 | #define X86_BUG_RETBLEED X86_BUG(27) /* CPU is affected by RETBleed */
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469 | 484 | #define X86_BUG_EIBRS_PBRSB X86_BUG(28) /* EIBRS is vulnerable to Post Barrier RSB Predictions */
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| 485 | +#define X86_BUG_SMT_RSB X86_BUG(29) /* CPU is vulnerable to Cross-Thread Return Address Predictions */ |
470 | 486 |
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471 | 487 | #endif /* _ASM_X86_CPUFEATURES_H */
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