@@ -337,7 +337,7 @@ static int emulate_std(struct pt_regs *regs, int frreg, int flop)
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: " r19 ", " r20 ", " r21 ", " r22 ", " r1 " );
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#else
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{
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- unsigned long valh = (val >> 32 ),vall = (val & 0xffffffffl );
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+ unsigned long valh = (val >> 32 ), vall = (val & 0xffffffffl );
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__asm__ __volatile__ (
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" mtsp %4, %%sr1\n"
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" zdep %2, 29, 2, %%r19\n"
@@ -473,7 +473,7 @@ void handle_unaligned(struct pt_regs *regs)
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case OPCODE_LDWA_I :
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case OPCODE_LDW_S :
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case OPCODE_LDWA_S :
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- ret = emulate_ldw (regs , R3 (regs -> iir ),0 );
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+ ret = emulate_ldw (regs , R3 (regs -> iir ), 0 );
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break ;
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case OPCODE_STH :
@@ -482,45 +482,45 @@ void handle_unaligned(struct pt_regs *regs)
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case OPCODE_STW :
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case OPCODE_STWA :
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- ret = emulate_stw (regs , R2 (regs -> iir ),0 );
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+ ret = emulate_stw (regs , R2 (regs -> iir ), 0 );
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break ;
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#ifdef CONFIG_64BIT
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case OPCODE_LDD_I :
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case OPCODE_LDDA_I :
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case OPCODE_LDD_S :
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case OPCODE_LDDA_S :
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- ret = emulate_ldd (regs , R3 (regs -> iir ),0 );
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+ ret = emulate_ldd (regs , R3 (regs -> iir ), 0 );
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break ;
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case OPCODE_STD :
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case OPCODE_STDA :
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- ret = emulate_std (regs , R2 (regs -> iir ),0 );
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+ ret = emulate_std (regs , R2 (regs -> iir ), 0 );
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break ;
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#endif
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case OPCODE_FLDWX :
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case OPCODE_FLDWS :
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case OPCODE_FLDWXR :
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case OPCODE_FLDWSR :
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- ret = emulate_ldw (regs ,FR3 (regs -> iir ),1 );
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+ ret = emulate_ldw (regs , FR3 (regs -> iir ), 1 );
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break ;
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case OPCODE_FLDDX :
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case OPCODE_FLDDS :
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- ret = emulate_ldd (regs ,R3 (regs -> iir ),1 );
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+ ret = emulate_ldd (regs , R3 (regs -> iir ), 1 );
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break ;
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case OPCODE_FSTWX :
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case OPCODE_FSTWS :
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case OPCODE_FSTWXR :
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case OPCODE_FSTWSR :
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- ret = emulate_stw (regs ,FR3 (regs -> iir ),1 );
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+ ret = emulate_stw (regs , FR3 (regs -> iir ), 1 );
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break ;
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case OPCODE_FSTDX :
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case OPCODE_FSTDS :
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- ret = emulate_std (regs ,R3 (regs -> iir ),1 );
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+ ret = emulate_std (regs , R3 (regs -> iir ), 1 );
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break ;
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case OPCODE_LDCD_I :
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