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Sung Joon Kimalexdeucher
Sung Joon Kim
authored and
alexdeucher
committed
drm/amd/display: Program plane color setting correctly
[why] There are some registers for plane color that are skipped programming on resume. Need to add those as part of the sequence. [how] Add new function hook for programming plane color control. Reviewed-by: Duncan Ma <duncan.ma@amd.com> Acked-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Sung Joon Kim <sungkim@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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4 files changed

+156
-2
lines changed

4 files changed

+156
-2
lines changed

‎drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -316,7 +316,7 @@ bool hubp3_program_surface_flip_and_addr(
316316
return true;
317317
}
318318

319-
static void hubp3_program_tiling(
319+
void hubp3_program_tiling(
320320
struct dcn20_hubp *hubp2,
321321
const union dc_tiling_info *info,
322322
const enum surface_pixel_format pixel_format)

‎drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -278,6 +278,11 @@ void hubp3_setup(
278278
struct _vcs_dpi_display_rq_regs_st *rq_regs,
279279
struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
280280

281+
void hubp3_program_tiling(
282+
struct dcn20_hubp *hubp2,
283+
const union dc_tiling_info *info,
284+
const enum surface_pixel_format pixel_format);
285+
281286
void hubp3_dcc_control(struct hubp *hubp, bool enable,
282287
enum hubp_ind_block_size blk_size);
283288

‎drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubp.c

Lines changed: 136 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -53,11 +53,146 @@ static void hubp35_init(struct hubp *hubp)
5353

5454
/*do nothing for now for dcn3.5 or later*/
5555
}
56+
57+
void hubp35_program_pixel_format(
58+
struct hubp *hubp,
59+
enum surface_pixel_format format)
60+
{
61+
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
62+
uint32_t green_bar = 1;
63+
uint32_t red_bar = 3;
64+
uint32_t blue_bar = 2;
65+
66+
/* swap for ABGR format */
67+
if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
68+
|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
69+
|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
70+
|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616
71+
|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
72+
red_bar = 2;
73+
blue_bar = 3;
74+
}
75+
76+
REG_UPDATE_3(HUBPRET_CONTROL,
77+
CROSSBAR_SRC_Y_G, green_bar,
78+
CROSSBAR_SRC_CB_B, blue_bar,
79+
CROSSBAR_SRC_CR_R, red_bar);
80+
81+
/* Mapping is same as ipp programming (cnvc) */
82+
83+
switch (format) {
84+
case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
85+
REG_UPDATE(DCSURF_SURFACE_CONFIG,
86+
SURFACE_PIXEL_FORMAT, 1);
87+
break;
88+
case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
89+
REG_UPDATE(DCSURF_SURFACE_CONFIG,
90+
SURFACE_PIXEL_FORMAT, 3);
91+
break;
92+
case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
93+
case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
94+
REG_UPDATE(DCSURF_SURFACE_CONFIG,
95+
SURFACE_PIXEL_FORMAT, 8);
96+
break;
97+
case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
98+
case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
99+
case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
100+
REG_UPDATE(DCSURF_SURFACE_CONFIG,
101+
SURFACE_PIXEL_FORMAT, 10);
102+
break;
103+
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
104+
case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /* we use crossbar already */
105+
REG_UPDATE(DCSURF_SURFACE_CONFIG,
106+
SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */
107+
break;
108+
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
109+
case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/
110+
REG_UPDATE(DCSURF_SURFACE_CONFIG,
111+
SURFACE_PIXEL_FORMAT, 24);
112+
break;
113+
114+
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
115+
REG_UPDATE(DCSURF_SURFACE_CONFIG,
116+
SURFACE_PIXEL_FORMAT, 65);
117+
break;
118+
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
119+
REG_UPDATE(DCSURF_SURFACE_CONFIG,
120+
SURFACE_PIXEL_FORMAT, 64);
121+
break;
122+
case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
123+
REG_UPDATE(DCSURF_SURFACE_CONFIG,
124+
SURFACE_PIXEL_FORMAT, 67);
125+
break;
126+
case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
127+
REG_UPDATE(DCSURF_SURFACE_CONFIG,
128+
SURFACE_PIXEL_FORMAT, 66);
129+
break;
130+
case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
131+
REG_UPDATE(DCSURF_SURFACE_CONFIG,
132+
SURFACE_PIXEL_FORMAT, 12);
133+
break;
134+
case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
135+
REG_UPDATE(DCSURF_SURFACE_CONFIG,
136+
SURFACE_PIXEL_FORMAT, 112);
137+
break;
138+
case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
139+
REG_UPDATE(DCSURF_SURFACE_CONFIG,
140+
SURFACE_PIXEL_FORMAT, 113);
141+
break;
142+
case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
143+
REG_UPDATE(DCSURF_SURFACE_CONFIG,
144+
SURFACE_PIXEL_FORMAT, 114);
145+
break;
146+
case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
147+
REG_UPDATE(DCSURF_SURFACE_CONFIG,
148+
SURFACE_PIXEL_FORMAT, 118);
149+
break;
150+
case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
151+
REG_UPDATE(DCSURF_SURFACE_CONFIG,
152+
SURFACE_PIXEL_FORMAT, 119);
153+
break;
154+
case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
155+
REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
156+
SURFACE_PIXEL_FORMAT, 116,
157+
ALPHA_PLANE_EN, 0);
158+
break;
159+
case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
160+
REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
161+
SURFACE_PIXEL_FORMAT, 116,
162+
ALPHA_PLANE_EN, 1);
163+
break;
164+
default:
165+
BREAK_TO_DEBUGGER();
166+
break;
167+
}
168+
169+
/* don't see the need of program the xbar in DCN 1.0 */
170+
}
171+
172+
void hubp35_program_surface_config(
173+
struct hubp *hubp,
174+
enum surface_pixel_format format,
175+
union dc_tiling_info *tiling_info,
176+
struct plane_size *plane_size,
177+
enum dc_rotation_angle rotation,
178+
struct dc_plane_dcc_param *dcc,
179+
bool horizontal_mirror,
180+
unsigned int compat_level)
181+
{
182+
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
183+
184+
hubp3_dcc_control_sienna_cichlid(hubp, dcc);
185+
hubp3_program_tiling(hubp2, tiling_info, format);
186+
hubp2_program_size(hubp, format, plane_size, dcc);
187+
hubp2_program_rotation(hubp, rotation, horizontal_mirror);
188+
hubp35_program_pixel_format(hubp, format);
189+
}
190+
56191
struct hubp_funcs dcn35_hubp_funcs = {
57192
.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
58193
.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
59194
.hubp_program_surface_flip_and_addr = hubp3_program_surface_flip_and_addr,
60-
.hubp_program_surface_config = hubp3_program_surface_config,
195+
.hubp_program_surface_config = hubp35_program_surface_config,
61196
.hubp_is_flip_pending = hubp2_is_flip_pending,
62197
.hubp_setup = hubp3_setup,
63198
.hubp_setup_interdependent = hubp2_setup_interdependent,

‎drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubp.h

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58,4 +58,18 @@ bool hubp35_construct(
5858

5959
void hubp35_set_fgcg(struct hubp *hubp, bool enable);
6060

61+
void hubp35_program_pixel_format(
62+
struct hubp *hubp,
63+
enum surface_pixel_format format);
64+
65+
void hubp35_program_surface_config(
66+
struct hubp *hubp,
67+
enum surface_pixel_format format,
68+
union dc_tiling_info *tiling_info,
69+
struct plane_size *plane_size,
70+
enum dc_rotation_angle rotation,
71+
struct dc_plane_dcc_param *dcc,
72+
bool horizontal_mirror,
73+
unsigned int compat_level);
74+
6175
#endif /* __DC_HUBP_DCN35_H__ */

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