Skip to content

Commit 98dcc6b

Browse files
finley1226mmind
authored andcommitted
clk: rockchip: rk3128: Fix aclk_peri_src's parent
According to the TRM there are no specific gpll_peri, cpll_peri, gpll_div2_peri or gpll_div3_peri gates, but a single clk_peri_src gate. Instead mux_clk_peri_src directly connects to the plls respectively the pll divider clocks. Fix this by creating a single gated composite. Also rename all occurrences of aclk_peri_src to clk_peri_src, since it is the parent for peri aclks, pclks and hclks. That name also matches the one used in the TRM. Fixes: f6022e8 ("clk: rockchip: add clock controller for rk3128") Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> [renamed aclk_peri_src -> clk_peri_src and added commit message] Signed-off-by: Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20231127181415.11735-4-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
1 parent c6c5a55 commit 98dcc6b

File tree

1 file changed

+7
-13
lines changed

1 file changed

+7
-13
lines changed

drivers/clk/rockchip/clk-rk3128.c

Lines changed: 7 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -138,7 +138,7 @@ PNAME(mux_pll_src_5plls_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3", "usb480
138138
PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "gpll_div2", "usb480m" };
139139
PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "gpll_div2" };
140140

141-
PNAME(mux_aclk_peri_src_p) = { "gpll_peri", "cpll_peri", "gpll_div2_peri", "gpll_div3_peri" };
141+
PNAME(mux_clk_peri_src_p) = { "gpll", "cpll", "gpll_div2", "gpll_div3" };
142142
PNAME(mux_mmc_src_p) = { "cpll", "gpll", "gpll_div2", "xin24m" };
143143
PNAME(mux_clk_cif_out_src_p) = { "clk_cif_src", "xin24m" };
144144
PNAME(mux_sclk_vop_src_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3" };
@@ -275,23 +275,17 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
275275
RK2928_CLKGATE_CON(0), 11, GFLAGS),
276276

277277
/* PD_PERI */
278-
GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,
278+
COMPOSITE(0, "clk_peri_src", mux_clk_peri_src_p, 0,
279+
RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS,
279280
RK2928_CLKGATE_CON(2), 0, GFLAGS),
280-
GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED,
281-
RK2928_CLKGATE_CON(2), 0, GFLAGS),
282-
GATE(0, "gpll_div2_peri", "gpll_div2", CLK_IGNORE_UNUSED,
283-
RK2928_CLKGATE_CON(2), 0, GFLAGS),
284-
GATE(0, "gpll_div3_peri", "gpll_div3", CLK_IGNORE_UNUSED,
285-
RK2928_CLKGATE_CON(2), 0, GFLAGS),
286-
COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0,
287-
RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS),
288-
COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
281+
282+
COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "clk_peri_src", 0,
289283
RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
290284
RK2928_CLKGATE_CON(2), 3, GFLAGS),
291-
COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0,
285+
COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "clk_peri_src", 0,
292286
RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
293287
RK2928_CLKGATE_CON(2), 2, GFLAGS),
294-
GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
288+
GATE(ACLK_PERI, "aclk_peri", "clk_peri_src", 0,
295289
RK2928_CLKGATE_CON(2), 1, GFLAGS),
296290

297291
GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,

0 commit comments

Comments
 (0)