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Merge tag 'pinctrl-v6.3-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control fixes from Linus Walleij: "Some pin control fixes for the v6.3 series. The most notable and urgent one is probably the AMD fix which affects AMD laptops, found by the Chromium people. Summary: - Fix up the Kconfig options for MediaTek MT7981 - Fix the irq domain name in the AT91-PIO4 driver - Fix some alternative muxing modes in the Ocelot driver - Allocate the GPIO numbers dynamically in the STM32 driver - Disable and mask interrupts on resume in the AMD driver - Fix a typo in the Qualcomm SM8550 pin control device tree bindings" * tag 'pinctrl-v6.3-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: dt-bindings: pinctrl: qcom,sm8550-lpass-lpi: allow input-enabled and bias-bus-hold pinctrl: amd: Disable and mask interrupts on resume pinctrl: stm32: use dynamic allocation of GPIO base pinctrl: ocelot: Fix alt mode for ocelot pinctrl: at91-pio4: fix domain name assignment pinctrl: mediatek: fix naming inconsistency pinctrl: mediatek: add missing options to PINCTRL_MT7981
2 parents ce0c237 + e4056e3 commit 93e2b01

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6 files changed

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Documentation/devicetree/bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -96,9 +96,11 @@ $defs:
9696
2: Lower Slew rate (slower edges)
9797
3: Reserved (No adjustments)
9898
99+
bias-bus-hold: true
99100
bias-pull-down: true
100101
bias-pull-up: true
101102
bias-disable: true
103+
input-enable: true
102104
output-high: true
103105
output-low: true
104106

drivers/pinctrl/mediatek/Kconfig

Lines changed: 23 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -45,35 +45,35 @@ config PINCTRL_MTK_PARIS
4545

4646
# For ARMv7 SoCs
4747
config PINCTRL_MT2701
48-
bool "Mediatek MT2701 pin control"
48+
bool "MediaTek MT2701 pin control"
4949
depends on MACH_MT7623 || MACH_MT2701 || COMPILE_TEST
5050
depends on OF
5151
default MACH_MT2701
5252
select PINCTRL_MTK
5353

5454
config PINCTRL_MT7623
55-
bool "Mediatek MT7623 pin control with generic binding"
55+
bool "MediaTek MT7623 pin control with generic binding"
5656
depends on MACH_MT7623 || COMPILE_TEST
5757
depends on OF
5858
default MACH_MT7623
5959
select PINCTRL_MTK_MOORE
6060

6161
config PINCTRL_MT7629
62-
bool "Mediatek MT7629 pin control"
62+
bool "MediaTek MT7629 pin control"
6363
depends on MACH_MT7629 || COMPILE_TEST
6464
depends on OF
6565
default MACH_MT7629
6666
select PINCTRL_MTK_MOORE
6767

6868
config PINCTRL_MT8135
69-
bool "Mediatek MT8135 pin control"
69+
bool "MediaTek MT8135 pin control"
7070
depends on MACH_MT8135 || COMPILE_TEST
7171
depends on OF
7272
default MACH_MT8135
7373
select PINCTRL_MTK
7474

7575
config PINCTRL_MT8127
76-
bool "Mediatek MT8127 pin control"
76+
bool "MediaTek MT8127 pin control"
7777
depends on MACH_MT8127 || COMPILE_TEST
7878
depends on OF
7979
default MACH_MT8127
@@ -88,33 +88,33 @@ config PINCTRL_MT2712
8888
select PINCTRL_MTK
8989

9090
config PINCTRL_MT6765
91-
tristate "Mediatek MT6765 pin control"
91+
tristate "MediaTek MT6765 pin control"
9292
depends on OF
9393
depends on ARM64 || COMPILE_TEST
9494
default ARM64 && ARCH_MEDIATEK
9595
select PINCTRL_MTK_PARIS
9696

9797
config PINCTRL_MT6779
98-
tristate "Mediatek MT6779 pin control"
98+
tristate "MediaTek MT6779 pin control"
9999
depends on OF
100100
depends on ARM64 || COMPILE_TEST
101101
default ARM64 && ARCH_MEDIATEK
102102
select PINCTRL_MTK_PARIS
103103
help
104104
Say yes here to support pin controller and gpio driver
105-
on Mediatek MT6779 SoC.
105+
on MediaTek MT6779 SoC.
106106
In MTK platform, we support virtual gpio and use it to
107107
map specific eint which doesn't have real gpio pin.
108108

109109
config PINCTRL_MT6795
110-
bool "Mediatek MT6795 pin control"
110+
bool "MediaTek MT6795 pin control"
111111
depends on OF
112112
depends on ARM64 || COMPILE_TEST
113113
default ARM64 && ARCH_MEDIATEK
114114
select PINCTRL_MTK_PARIS
115115

116116
config PINCTRL_MT6797
117-
bool "Mediatek MT6797 pin control"
117+
bool "MediaTek MT6797 pin control"
118118
depends on OF
119119
depends on ARM64 || COMPILE_TEST
120120
default ARM64 && ARCH_MEDIATEK
@@ -128,40 +128,42 @@ config PINCTRL_MT7622
128128
select PINCTRL_MTK_MOORE
129129

130130
config PINCTRL_MT7981
131-
bool "Mediatek MT7981 pin control"
131+
bool "MediaTek MT7981 pin control"
132132
depends on OF
133+
depends on ARM64 || COMPILE_TEST
134+
default ARM64 && ARCH_MEDIATEK
133135
select PINCTRL_MTK_MOORE
134136

135137
config PINCTRL_MT7986
136-
bool "Mediatek MT7986 pin control"
138+
bool "MediaTek MT7986 pin control"
137139
depends on OF
138140
depends on ARM64 || COMPILE_TEST
139141
default ARM64 && ARCH_MEDIATEK
140142
select PINCTRL_MTK_MOORE
141143

142144
config PINCTRL_MT8167
143-
bool "Mediatek MT8167 pin control"
145+
bool "MediaTek MT8167 pin control"
144146
depends on OF
145147
depends on ARM64 || COMPILE_TEST
146148
default ARM64 && ARCH_MEDIATEK
147149
select PINCTRL_MTK
148150

149151
config PINCTRL_MT8173
150-
bool "Mediatek MT8173 pin control"
152+
bool "MediaTek MT8173 pin control"
151153
depends on OF
152154
depends on ARM64 || COMPILE_TEST
153155
default ARM64 && ARCH_MEDIATEK
154156
select PINCTRL_MTK
155157

156158
config PINCTRL_MT8183
157-
bool "Mediatek MT8183 pin control"
159+
bool "MediaTek MT8183 pin control"
158160
depends on OF
159161
depends on ARM64 || COMPILE_TEST
160162
default ARM64 && ARCH_MEDIATEK
161163
select PINCTRL_MTK_PARIS
162164

163165
config PINCTRL_MT8186
164-
bool "Mediatek MT8186 pin control"
166+
bool "MediaTek MT8186 pin control"
165167
depends on OF
166168
depends on ARM64 || COMPILE_TEST
167169
default ARM64 && ARCH_MEDIATEK
@@ -180,36 +182,36 @@ config PINCTRL_MT8188
180182
map specific eint which doesn't have real gpio pin.
181183

182184
config PINCTRL_MT8192
183-
bool "Mediatek MT8192 pin control"
185+
bool "MediaTek MT8192 pin control"
184186
depends on OF
185187
depends on ARM64 || COMPILE_TEST
186188
default ARM64 && ARCH_MEDIATEK
187189
select PINCTRL_MTK_PARIS
188190

189191
config PINCTRL_MT8195
190-
bool "Mediatek MT8195 pin control"
192+
bool "MediaTek MT8195 pin control"
191193
depends on OF
192194
depends on ARM64 || COMPILE_TEST
193195
default ARM64 && ARCH_MEDIATEK
194196
select PINCTRL_MTK_PARIS
195197

196198
config PINCTRL_MT8365
197-
bool "Mediatek MT8365 pin control"
199+
bool "MediaTek MT8365 pin control"
198200
depends on OF
199201
depends on ARM64 || COMPILE_TEST
200202
default ARM64 && ARCH_MEDIATEK
201203
select PINCTRL_MTK
202204

203205
config PINCTRL_MT8516
204-
bool "Mediatek MT8516 pin control"
206+
bool "MediaTek MT8516 pin control"
205207
depends on OF
206208
depends on ARM64 || COMPILE_TEST
207209
default ARM64 && ARCH_MEDIATEK
208210
select PINCTRL_MTK
209211

210212
# For PMIC
211213
config PINCTRL_MT6397
212-
bool "Mediatek MT6397 pin control"
214+
bool "MediaTek MT6397 pin control"
213215
depends on MFD_MT6397 || COMPILE_TEST
214216
depends on OF
215217
default MFD_MT6397

drivers/pinctrl/pinctrl-amd.c

Lines changed: 20 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -872,32 +872,34 @@ static const struct pinconf_ops amd_pinconf_ops = {
872872
.pin_config_group_set = amd_pinconf_group_set,
873873
};
874874

875-
static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
875+
static void amd_gpio_irq_init_pin(struct amd_gpio *gpio_dev, int pin)
876876
{
877-
struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
877+
const struct pin_desc *pd;
878878
unsigned long flags;
879879
u32 pin_reg, mask;
880-
int i;
881880

882881
mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
883882
BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) |
884883
BIT(WAKE_CNTRL_OFF_S4);
885884

886-
for (i = 0; i < desc->npins; i++) {
887-
int pin = desc->pins[i].number;
888-
const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
889-
890-
if (!pd)
891-
continue;
885+
pd = pin_desc_get(gpio_dev->pctrl, pin);
886+
if (!pd)
887+
return;
892888

893-
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
889+
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
890+
pin_reg = readl(gpio_dev->base + pin * 4);
891+
pin_reg &= ~mask;
892+
writel(pin_reg, gpio_dev->base + pin * 4);
893+
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
894+
}
894895

895-
pin_reg = readl(gpio_dev->base + i * 4);
896-
pin_reg &= ~mask;
897-
writel(pin_reg, gpio_dev->base + i * 4);
896+
static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
897+
{
898+
struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
899+
int i;
898900

899-
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
900-
}
901+
for (i = 0; i < desc->npins; i++)
902+
amd_gpio_irq_init_pin(gpio_dev, i);
901903
}
902904

903905
#ifdef CONFIG_PM_SLEEP
@@ -950,8 +952,10 @@ static int amd_gpio_resume(struct device *dev)
950952
for (i = 0; i < desc->npins; i++) {
951953
int pin = desc->pins[i].number;
952954

953-
if (!amd_gpio_should_save(gpio_dev, pin))
955+
if (!amd_gpio_should_save(gpio_dev, pin)) {
956+
amd_gpio_irq_init_pin(gpio_dev, pin);
954957
continue;
958+
}
955959

956960
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
957961
gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING;

drivers/pinctrl/pinctrl-at91-pio4.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1206,7 +1206,6 @@ static int atmel_pinctrl_probe(struct platform_device *pdev)
12061206
dev_err(dev, "can't add the irq domain\n");
12071207
return -ENODEV;
12081208
}
1209-
atmel_pioctrl->irq_domain->name = "atmel gpio";
12101209

12111210
for (i = 0; i < atmel_pioctrl->npins; i++) {
12121211
int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i);

drivers/pinctrl/pinctrl-ocelot.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1204,7 +1204,7 @@ static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
12041204
regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
12051205
BIT(p), f << p);
12061206
regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
1207-
BIT(p), f << (p - 1));
1207+
BIT(p), (f >> 1) << p);
12081208

12091209
return 0;
12101210
}

drivers/pinctrl/stm32/pinctrl-stm32.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1330,7 +1330,7 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode
13301330
if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr))
13311331
bank_ioport_nr = bank_nr;
13321332

1333-
bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1333+
bank->gpio_chip.base = -1;
13341334

13351335
bank->gpio_chip.ngpio = npins;
13361336
bank->gpio_chip.fwnode = fwnode;

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