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Merge tag 'irq-core-2022-03-21' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull interrupt updates from Thomas Gleixner: "Core code: - Provide generic_handle_irq_safe() which can be invoked from any context (hard interrupt or threaded). This allows to remove ugly workarounds in drivers all over the place. - Use generic_handle_irq_safe() in the affected drivers. - The usual cleanups and improvements. Interrupt chip drivers: - Support for new interrupt chips or not yet supported variants: STM32MP14, Meson GPIO, Apple M1 PMU, Apple M1 AICv2, Qualcomm MPM - Convert the Xilinx driver to generic interrupt domains - Cleanup the irq_chip::name handling - The usual cleanups and improvements all over the place" * tag 'irq-core-2022-03-21' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (52 commits) irqchip: Add Qualcomm MPM controller driver dt-bindings: interrupt-controller: Add Qualcomm MPM support irqchip/apple-aic: Add support for AICv2 irqchip/apple-aic: Support multiple dies irqchip/apple-aic: Dynamically compute register offsets irqchip/apple-aic: Switch to irq_domain_create_tree and sparse hwirqs irqchip/apple-aic: Add Fast IPI support dt-bindings: interrupt-controller: apple,aic2: New binding for AICv2 PCI: apple: Change MSI handling to handle 4-cell AIC fwspec form irqchip/apple-aic: Fix cpumask allocation for FIQs irqchip/meson-gpio: Add support for meson s4 SoCs irqchip/meson-gpio: add select trigger type callback irqchip/meson-gpio: support more than 8 channels gpio irq dt-bindings: interrupt-controller: New binding for Meson-S4 SoCs irqchip/xilinx: Switch to GENERIC_IRQ_MULTI_HANDLER staging: greybus: gpio: Use generic_handle_irq_safe(). net: usb: lan78xx: Use generic_handle_irq_safe(). mfd: ezx-pcap: Use generic_handle_irq_safe(). misc: hi6421-spmi-pmic: Use generic_handle_irq_safe(). irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode ...
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‎Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt

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@@ -18,6 +18,7 @@ Required properties:
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"amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)
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"amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3)
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"amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L)
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"amlogic,meson-s4-gpio-intc" for S4 SoCs (S802X2, S905Y4, S805X2G, S905W2)
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- reg : Specifies base physical address and size of the registers.
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- interrupt-controller : Identifies the node as an interrupt controller.
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- #interrupt-cells : Specifies the number of cells needed to encode an

‎Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Apple Interrupt Controller 2
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maintainers:
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- Hector Martin <marcan@marcan.st>
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description: |
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The Apple Interrupt Controller 2 is a simple interrupt controller present on
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Apple ARM SoC platforms starting with t600x (M1 Pro and Max).
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It provides the following features:
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- Level-triggered hardware IRQs wired to SoC blocks
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- Single mask bit per IRQ
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- Automatic masking on event delivery (auto-ack)
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- Software triggering (ORed with hw line)
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- Automatic prioritization (single event/ack register per CPU, lower IRQs =
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higher priority)
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- Automatic masking on ack
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- Support for multiple dies
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This device also represents the FIQ interrupt sources on platforms using AIC,
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which do not go through a discrete interrupt controller. It also handles
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FIQ-based Fast IPIs.
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properties:
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compatible:
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items:
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- const: apple,t6000-aic
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- const: apple,aic2
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interrupt-controller: true
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'#interrupt-cells':
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const: 4
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description: |
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The 1st cell contains the interrupt type:
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- 0: Hardware IRQ
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- 1: FIQ
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The 2nd cell contains the die ID.
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The next cell contains the interrupt number.
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- HW IRQs: interrupt number
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- FIQs:
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- 0: physical HV timer
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- 1: virtual HV timer
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- 2: physical guest timer
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- 3: virtual guest timer
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The last cell contains the interrupt flags. This is normally
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IRQ_TYPE_LEVEL_HIGH (4).
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reg:
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items:
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- description: Address and size of the main AIC2 registers.
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- description: Address and size of the AIC2 Event register.
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reg-names:
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items:
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- const: core
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- const: event
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power-domains:
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maxItems: 1
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required:
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- compatible
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- '#interrupt-cells'
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- interrupt-controller
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- reg
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- reg-names
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additionalProperties: false
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allOf:
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- $ref: /schemas/interrupt-controller.yaml#
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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aic: interrupt-controller@28e100000 {
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compatible = "apple,t6000-aic", "apple,aic2";
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#interrupt-cells = <4>;
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interrupt-controller;
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reg = <0x2 0x8e100000 0x0 0xc000>,
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<0x2 0x8e10c000 0x0 0x4>;
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reg-names = "core", "event";
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};
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};

‎Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/qcom,mpm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcom MPM Interrupt Controller
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maintainers:
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- Shawn Guo <shawn.guo@linaro.org>
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description:
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Qualcomm Technologies Inc. SoCs based on the RPM architecture have a
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MSM Power Manager (MPM) that is in always-on domain. In addition to managing
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resources during sleep, the hardware also has an interrupt controller that
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monitors the interrupts when the system is asleep, wakes up the APSS when
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one of these interrupts occur and replays it to GIC interrupt controller
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after GIC becomes operational.
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allOf:
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- $ref: /schemas/interrupt-controller.yaml#
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properties:
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compatible:
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items:
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- const: qcom,mpm
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reg:
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maxItems: 1
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description:
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Specifies the base address and size of vMPM registers in RPM MSG RAM.
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interrupts:
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maxItems: 1
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description:
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Specify the IRQ used by RPM to wakeup APSS.
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mboxes:
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maxItems: 1
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description:
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Specify the mailbox used to notify RPM for writing vMPM registers.
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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description:
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The first cell is the MPM pin number for the interrupt, and the second
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is the trigger type.
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qcom,mpm-pin-count:
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description:
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Specify the total MPM pin count that a SoC supports.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,mpm-pin-map:
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description:
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A set of MPM pin numbers and the corresponding GIC SPIs.
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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items:
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items:
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- description: MPM pin number
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- description: GIC SPI number for the MPM pin
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required:
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- compatible
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- reg
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- interrupts
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- mboxes
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- interrupt-controller
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- '#interrupt-cells'
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- qcom,mpm-pin-count
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- qcom,mpm-pin-map
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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mpm: interrupt-controller@45f01b8 {
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compatible = "qcom,mpm";
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interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
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reg = <0x45f01b8 0x1000>;
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mboxes = <&apcs_glb 1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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qcom,mpm-pin-count = <96>;
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qcom,mpm-pin-map = <2 275>,
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<5 296>,
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<12 422>,
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<24 79>,
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<86 183>,
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<90 260>,
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<91 260>;
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};

‎Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml

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- items:
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- enum:
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- st,stm32mp1-exti
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- st,stm32mp13-exti
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- const: syscon
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"#interrupt-cells":

‎MAINTAINERS

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F: Documentation/devicetree/bindings/arm/apple.yaml
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F: Documentation/devicetree/bindings/arm/apple/*
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F: Documentation/devicetree/bindings/i2c/apple,i2c.yaml
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F: Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml
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F: Documentation/devicetree/bindings/interrupt-controller/apple,*
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F: Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml
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F: Documentation/devicetree/bindings/pci/apple,pcie.yaml
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F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml

‎arch/microblaze/Kconfig

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select SET_FS
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select ZONE_DMA
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select TRACE_IRQFLAGS_SUPPORT
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select GENERIC_IRQ_MULTI_HANDLER
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select HANDLE_DOMAIN_IRQ
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# Endianness selection
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choice

‎arch/microblaze/include/asm/irq.h

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struct pt_regs;
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extern void do_IRQ(struct pt_regs *regs);
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/* should be defined in each interrupt controller driver */
15-
extern unsigned int xintc_get_irq(void);
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#endif /* _ASM_MICROBLAZE_IRQ_H */

‎arch/microblaze/kernel/irq.c

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#include <linux/irqchip.h>
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#include <linux/of_irq.h>
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static u32 concurrent_irq;
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void __irq_entry do_IRQ(struct pt_regs *regs)
2624
{
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unsigned int irq;
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struct pt_regs *old_regs = set_irq_regs(regs);
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trace_hardirqs_off();
3027

3128
irq_enter();
32-
irq = xintc_get_irq();
33-
next_irq:
34-
BUG_ON(!irq);
35-
generic_handle_irq(irq);
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irq = xintc_get_irq();
38-
if (irq != -1U) {
39-
pr_debug("next irq: %d\n", irq);
40-
++concurrent_irq;
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goto next_irq;
42-
}
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handle_arch_irq(regs);
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irq_exit();
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set_irq_regs(old_regs);
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trace_hardirqs_on();

‎drivers/gpio/gpio-mt7621.c

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rg->chip.offset = bank * MTK_BANK_WIDTH;
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rg->irq_chip.name = dev_name(dev);
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rg->irq_chip.parent_device = dev;
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rg->irq_chip.irq_unmask = mediatek_gpio_irq_unmask;
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rg->irq_chip.irq_mask = mediatek_gpio_irq_mask;
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rg->irq_chip.irq_mask_ack = mediatek_gpio_irq_mask;

‎drivers/gpio/gpio-omap.c

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@@ -986,7 +986,8 @@ static void omap_gpio_mod_init(struct gpio_bank *bank)
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writel_relaxed(0, base + bank->regs->ctrl);
987987
}
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989-
static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
989+
static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc,
990+
struct device *pm_dev)
990991
{
991992
struct gpio_irq_chip *irq;
992993
static int gpio;
@@ -1052,6 +1053,7 @@ static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
10521053
if (ret)
10531054
return dev_err_probe(bank->chip.parent, ret, "Could not register gpio chip\n");
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1056+
irq_domain_set_pm_device(bank->chip.irq.domain, pm_dev);
10551057
ret = devm_request_irq(bank->chip.parent, bank->irq,
10561058
omap_gpio_irq_handler,
10571059
0, dev_name(bank->chip.parent), bank);
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14021404
irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
14031405
irqc->name = dev_name(&pdev->dev);
14041406
irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
1405-
irqc->parent_device = dev;
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14071408
bank->irq = platform_get_irq(pdev, 0);
14081409
if (bank->irq <= 0) {
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14671468
omap_gpio_mod_init(bank);
14681469

1469-
ret = omap_gpio_chip_init(bank, irqc);
1470+
ret = omap_gpio_chip_init(bank, irqc, dev);
14701471
if (ret) {
14711472
pm_runtime_put_sync(dev);
14721473
pm_runtime_disable(dev);

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