@@ -102,6 +102,7 @@ struct __guc_capture_parsed_output {
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* A 64 bit register define requires 2 consecutive entries,
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* with low dword first and hi dword the second.
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* 2. Register name: null for incompleted define
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+ * 3. Incorrect order will trigger XE_WARN.
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*/
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#define COMMON_XELP_BASE_GLOBAL \
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{ FORCEWAKE_GT, REG_32BIT, 0, 0, "FORCEWAKE_GT"}
@@ -1675,10 +1676,10 @@ snapshot_print_by_list_order(struct xe_hw_engine_snapshot *snapshot, struct drm_
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struct xe_devcoredump * devcoredump = & xe -> devcoredump ;
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struct xe_devcoredump_snapshot * devcore_snapshot = & devcoredump -> snapshot ;
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struct gcap_reg_list_info * reginfo = NULL ;
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- u32 last_value , i ;
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- bool is_ext ;
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+ u32 i , last_value = 0 ;
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+ bool is_ext , low32_ready = false ;
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- if (!list || list -> num_regs == 0 )
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+ if (!list || ! list -> list || list -> num_regs == 0 )
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return ;
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XE_WARN_ON (!devcore_snapshot -> matched_node );
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@@ -1701,29 +1702,75 @@ snapshot_print_by_list_order(struct xe_hw_engine_snapshot *snapshot, struct drm_
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continue ;
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value = reg -> value ;
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- if (reg_desc -> data_type == REG_64BIT_LOW_DW ) {
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+ switch (reg_desc -> data_type ) {
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+ case REG_64BIT_LOW_DW :
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last_value = value ;
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+
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+ /*
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+ * A 64 bit register define requires 2 consecutive
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+ * entries in register list, with low dword first
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+ * and hi dword the second, like:
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+ * { XXX_REG_LO(0), REG_64BIT_LOW_DW, 0, 0, NULL},
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+ * { XXX_REG_HI(0), REG_64BIT_HI_DW, 0, 0, "XXX_REG"},
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+ *
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+ * Incorrect order will trigger XE_WARN.
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+ *
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+ * Possible double low here, for example:
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+ * { XXX_REG_LO(0), REG_64BIT_LOW_DW, 0, 0, NULL},
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+ * { XXX_REG_LO(0), REG_64BIT_LOW_DW, 0, 0, NULL},
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+ */
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+ XE_WARN_ON (low32_ready );
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+ low32_ready = true;
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/* Low 32 bit dword saved, continue for high 32 bit */
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- continue ;
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- } else if (reg_desc -> data_type == REG_64BIT_HI_DW ) {
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+ break ;
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+
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+ case REG_64BIT_HI_DW : {
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u64 value_qw = ((u64 )value << 32 ) | last_value ;
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+ /*
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+ * Incorrect 64bit register order. Possible missing low.
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+ * for example:
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+ * { XXX_REG(0), REG_32BIT, 0, 0, NULL},
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+ * { XXX_REG_HI(0), REG_64BIT_HI_DW, 0, 0, NULL},
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+ */
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+ XE_WARN_ON (!low32_ready );
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+ low32_ready = false;
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+
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drm_printf (p , "\t%s: 0x%016llx\n" , reg_desc -> regname , value_qw );
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- continue ;
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+ break ;
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}
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- if (is_ext ) {
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- int dss , group , instance ;
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+ case REG_32BIT :
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+ /*
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+ * Incorrect 64bit register order. Possible missing high.
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+ * for example:
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+ * { XXX_REG_LO(0), REG_64BIT_LOW_DW, 0, 0, NULL},
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+ * { XXX_REG(0), REG_32BIT, 0, 0, "XXX_REG"},
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+ */
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+ XE_WARN_ON (low32_ready );
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+
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+ if (is_ext ) {
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+ int dss , group , instance ;
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- group = FIELD_GET (GUC_REGSET_STEERING_GROUP , reg_desc -> flags );
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- instance = FIELD_GET (GUC_REGSET_STEERING_INSTANCE , reg_desc -> flags );
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- dss = xe_gt_mcr_steering_info_to_dss_id (gt , group , instance );
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+ group = FIELD_GET (GUC_REGSET_STEERING_GROUP , reg_desc -> flags );
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+ instance = FIELD_GET (GUC_REGSET_STEERING_INSTANCE , reg_desc -> flags );
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+ dss = xe_gt_mcr_steering_info_to_dss_id (gt , group , instance );
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- drm_printf (p , "\t%s[%u]: 0x%08x\n" , reg_desc -> regname , dss , value );
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- } else {
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- drm_printf (p , "\t%s: 0x%08x\n" , reg_desc -> regname , value );
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+ drm_printf (p , "\t%s[%u]: 0x%08x\n" , reg_desc -> regname , dss , value );
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+ } else {
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+ drm_printf (p , "\t%s: 0x%08x\n" , reg_desc -> regname , value );
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+ }
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+ break ;
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}
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}
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+
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+ /*
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+ * Incorrect 64bit register order. Possible missing high.
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+ * for example:
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+ * { XXX_REG_LO(0), REG_64BIT_LOW_DW, 0, 0, NULL},
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+ * } // <- Register list end
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+ */
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+ XE_WARN_ON (low32_ready );
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}
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/**
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