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Merge tag 'clk-imx-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx
Pull i.MX clk driver updates from Abel Vesa: - Add missing AXI clock to the i.MX8MP AUDIOMIX in dt-bindings schema - Fix DSP and OCRAM_A parent clocks in i.MX8MP AUDIOMIX clock provider - Document vendor specific operating-mode property in i.MX8M clock provider dt-bindings schema - Apply overdrive/nominal constraints based on DT property in i.MX8MP clock provider * tag 'clk-imx-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux: clk: imx8mp: inform CCF of maximum frequency of clocks dt-bindings: clock: imx8m: document nominal/overdrive properties clk: clk-imx8mp-audiomix: fix dsp/ocram_a clock parents dt-bindings: clock: imx8mp: add axi clock
2 parents 2014c95 + 06a61b5 commit 8fbf3d4

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-7
lines changed

4 files changed

+168
-7
lines changed

‎Documentation/devicetree/bindings/clock/imx8m-clock.yaml

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,13 @@ properties:
4343
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8m-clock.h
4444
for the full list of i.MX8M clock IDs.
4545

46+
fsl,operating-mode:
47+
$ref: /schemas/types.yaml#/definitions/string
48+
enum: [nominal, overdrive]
49+
description:
50+
The operating mode of the SoC. This affects the maximum clock rates that
51+
can safely be configured by the clock controller.
52+
4653
required:
4754
- compatible
4855
- reg
@@ -109,6 +116,7 @@ examples:
109116
<&clk_ext3>, <&clk_ext4>;
110117
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
111118
"clk_ext3", "clk_ext4";
119+
fsl,operating-mode = "nominal";
112120
};
113121
114122
- |

‎Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -24,8 +24,8 @@ properties:
2424
maxItems: 1
2525

2626
clocks:
27-
minItems: 7
28-
maxItems: 7
27+
minItems: 8
28+
maxItems: 8
2929

3030
clock-names:
3131
items:
@@ -36,6 +36,7 @@ properties:
3636
- const: sai5
3737
- const: sai6
3838
- const: sai7
39+
- const: axi
3940

4041
'#clock-cells':
4142
const: 1
@@ -72,10 +73,11 @@ examples:
7273
<&clk IMX8MP_CLK_SAI3>,
7374
<&clk IMX8MP_CLK_SAI5>,
7475
<&clk IMX8MP_CLK_SAI6>,
75-
<&clk IMX8MP_CLK_SAI7>;
76+
<&clk IMX8MP_CLK_SAI7>,
77+
<&clk IMX8MP_CLK_AUDIO_AXI_ROOT>;
7678
clock-names = "ahb",
7779
"sai1", "sai2", "sai3",
78-
"sai5", "sai6", "sai7";
80+
"sai5", "sai6", "sai7", "axi";
7981
power-domains = <&pgc_audio>;
8082
};
8183

‎drivers/clk/imx/clk-imx8mp-audiomix.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -180,14 +180,14 @@ static struct clk_imx8mp_audiomix_sel sels[] = {
180180
CLK_GATE("asrc", ASRC_IPG),
181181
CLK_GATE("pdm", PDM_IPG),
182182
CLK_GATE("earc", EARC_IPG),
183-
CLK_GATE("ocrama", OCRAMA_IPG),
183+
CLK_GATE_PARENT("ocrama", OCRAMA_IPG, "axi"),
184184
CLK_GATE("aud2htx", AUD2HTX_IPG),
185185
CLK_GATE_PARENT("earc_phy", EARC_PHY, "sai_pll_out_div2"),
186186
CLK_GATE("sdma2", SDMA2_ROOT),
187187
CLK_GATE("sdma3", SDMA3_ROOT),
188188
CLK_GATE("spba2", SPBA2_ROOT),
189-
CLK_GATE("dsp", DSP_ROOT),
190-
CLK_GATE("dspdbg", DSPDBG_ROOT),
189+
CLK_GATE_PARENT("dsp", DSP_ROOT, "axi"),
190+
CLK_GATE_PARENT("dspdbg", DSPDBG_ROOT, "axi"),
191191
CLK_GATE("edma", EDMA_ROOT),
192192
CLK_GATE_PARENT("audpll", AUDPLL_ROOT, "osc_24m"),
193193
CLK_GATE("mu2", MU2_ROOT),

‎drivers/clk/imx/clk-imx8mp.c

Lines changed: 151 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88
#include <linux/err.h>
99
#include <linux/io.h>
1010
#include <linux/module.h>
11+
#include <linux/units.h>
1112
#include <linux/of_address.h>
1213
#include <linux/platform_device.h>
1314
#include <linux/slab.h>
@@ -406,11 +407,151 @@ static const char * const imx8mp_clkout_sels[] = {"audio_pll1_out", "audio_pll2_
406407
static struct clk_hw **hws;
407408
static struct clk_hw_onecell_data *clk_hw_data;
408409

410+
struct imx8mp_clock_constraints {
411+
unsigned int clkid;
412+
u32 maxrate;
413+
};
414+
415+
/*
416+
* Below tables are taken from IMX8MPCEC Rev. 2.1, 07/2023
417+
* Table 13. Maximum frequency of modules.
418+
* Probable typos fixed are marked with a comment.
419+
*/
420+
static const struct imx8mp_clock_constraints imx8mp_clock_common_constraints[] = {
421+
{ IMX8MP_CLK_A53_DIV, 1000 * HZ_PER_MHZ },
422+
{ IMX8MP_CLK_ENET_AXI, 266666667 }, /* Datasheet claims 266MHz */
423+
{ IMX8MP_CLK_NAND_USDHC_BUS, 266666667 }, /* Datasheet claims 266MHz */
424+
{ IMX8MP_CLK_MEDIA_APB, 200 * HZ_PER_MHZ },
425+
{ IMX8MP_CLK_HDMI_APB, 133333333 }, /* Datasheet claims 133MHz */
426+
{ IMX8MP_CLK_ML_AXI, 800 * HZ_PER_MHZ },
427+
{ IMX8MP_CLK_AHB, 133333333 },
428+
{ IMX8MP_CLK_IPG_ROOT, 66666667 },
429+
{ IMX8MP_CLK_AUDIO_AHB, 400 * HZ_PER_MHZ },
430+
{ IMX8MP_CLK_MEDIA_DISP2_PIX, 170 * HZ_PER_MHZ },
431+
{ IMX8MP_CLK_DRAM_ALT, 666666667 },
432+
{ IMX8MP_CLK_DRAM_APB, 200 * HZ_PER_MHZ },
433+
{ IMX8MP_CLK_CAN1, 80 * HZ_PER_MHZ },
434+
{ IMX8MP_CLK_CAN2, 80 * HZ_PER_MHZ },
435+
{ IMX8MP_CLK_PCIE_AUX, 10 * HZ_PER_MHZ },
436+
{ IMX8MP_CLK_I2C5, 66666667 }, /* Datasheet claims 66MHz */
437+
{ IMX8MP_CLK_I2C6, 66666667 }, /* Datasheet claims 66MHz */
438+
{ IMX8MP_CLK_SAI1, 66666667 }, /* Datasheet claims 66MHz */
439+
{ IMX8MP_CLK_SAI2, 66666667 }, /* Datasheet claims 66MHz */
440+
{ IMX8MP_CLK_SAI3, 66666667 }, /* Datasheet claims 66MHz */
441+
{ IMX8MP_CLK_SAI5, 66666667 }, /* Datasheet claims 66MHz */
442+
{ IMX8MP_CLK_SAI6, 66666667 }, /* Datasheet claims 66MHz */
443+
{ IMX8MP_CLK_ENET_QOS, 125 * HZ_PER_MHZ },
444+
{ IMX8MP_CLK_ENET_QOS_TIMER, 200 * HZ_PER_MHZ },
445+
{ IMX8MP_CLK_ENET_REF, 125 * HZ_PER_MHZ },
446+
{ IMX8MP_CLK_ENET_TIMER, 125 * HZ_PER_MHZ },
447+
{ IMX8MP_CLK_ENET_PHY_REF, 125 * HZ_PER_MHZ },
448+
{ IMX8MP_CLK_NAND, 500 * HZ_PER_MHZ },
449+
{ IMX8MP_CLK_QSPI, 400 * HZ_PER_MHZ },
450+
{ IMX8MP_CLK_USDHC1, 400 * HZ_PER_MHZ },
451+
{ IMX8MP_CLK_USDHC2, 400 * HZ_PER_MHZ },
452+
{ IMX8MP_CLK_I2C1, 66666667 }, /* Datasheet claims 66MHz */
453+
{ IMX8MP_CLK_I2C2, 66666667 }, /* Datasheet claims 66MHz */
454+
{ IMX8MP_CLK_I2C3, 66666667 }, /* Datasheet claims 66MHz */
455+
{ IMX8MP_CLK_I2C4, 66666667 }, /* Datasheet claims 66MHz */
456+
{ IMX8MP_CLK_UART1, 80 * HZ_PER_MHZ },
457+
{ IMX8MP_CLK_UART2, 80 * HZ_PER_MHZ },
458+
{ IMX8MP_CLK_UART3, 80 * HZ_PER_MHZ },
459+
{ IMX8MP_CLK_UART4, 80 * HZ_PER_MHZ },
460+
{ IMX8MP_CLK_ECSPI1, 80 * HZ_PER_MHZ },
461+
{ IMX8MP_CLK_ECSPI2, 80 * HZ_PER_MHZ },
462+
{ IMX8MP_CLK_PWM1, 66666667 }, /* Datasheet claims 66MHz */
463+
{ IMX8MP_CLK_PWM2, 66666667 }, /* Datasheet claims 66MHz */
464+
{ IMX8MP_CLK_PWM3, 66666667 }, /* Datasheet claims 66MHz */
465+
{ IMX8MP_CLK_PWM4, 66666667 }, /* Datasheet claims 66MHz */
466+
{ IMX8MP_CLK_GPT1, 100 * HZ_PER_MHZ },
467+
{ IMX8MP_CLK_GPT2, 100 * HZ_PER_MHZ },
468+
{ IMX8MP_CLK_GPT3, 100 * HZ_PER_MHZ },
469+
{ IMX8MP_CLK_GPT4, 100 * HZ_PER_MHZ },
470+
{ IMX8MP_CLK_GPT5, 100 * HZ_PER_MHZ },
471+
{ IMX8MP_CLK_GPT6, 100 * HZ_PER_MHZ },
472+
{ IMX8MP_CLK_WDOG, 66666667 }, /* Datasheet claims 66MHz */
473+
{ IMX8MP_CLK_IPP_DO_CLKO1, 200 * HZ_PER_MHZ },
474+
{ IMX8MP_CLK_IPP_DO_CLKO2, 200 * HZ_PER_MHZ },
475+
{ IMX8MP_CLK_HDMI_REF_266M, 266 * HZ_PER_MHZ },
476+
{ IMX8MP_CLK_USDHC3, 400 * HZ_PER_MHZ },
477+
{ IMX8MP_CLK_MEDIA_MIPI_PHY1_REF, 300 * HZ_PER_MHZ },
478+
{ IMX8MP_CLK_MEDIA_DISP1_PIX, 250 * HZ_PER_MHZ },
479+
{ IMX8MP_CLK_MEDIA_CAM2_PIX, 277 * HZ_PER_MHZ },
480+
{ IMX8MP_CLK_MEDIA_LDB, 595 * HZ_PER_MHZ },
481+
{ IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE, 200 * HZ_PER_MHZ },
482+
{ IMX8MP_CLK_ECSPI3, 80 * HZ_PER_MHZ },
483+
{ IMX8MP_CLK_PDM, 200 * HZ_PER_MHZ },
484+
{ IMX8MP_CLK_SAI7, 66666667 }, /* Datasheet claims 66MHz */
485+
{ IMX8MP_CLK_MAIN_AXI, 400 * HZ_PER_MHZ },
486+
{ /* Sentinel */ }
487+
};
488+
489+
static const struct imx8mp_clock_constraints imx8mp_clock_nominal_constraints[] = {
490+
{ IMX8MP_CLK_M7_CORE, 600 * HZ_PER_MHZ },
491+
{ IMX8MP_CLK_ML_CORE, 800 * HZ_PER_MHZ },
492+
{ IMX8MP_CLK_GPU3D_CORE, 800 * HZ_PER_MHZ },
493+
{ IMX8MP_CLK_GPU3D_SHADER_CORE, 800 * HZ_PER_MHZ },
494+
{ IMX8MP_CLK_GPU2D_CORE, 800 * HZ_PER_MHZ },
495+
{ IMX8MP_CLK_AUDIO_AXI_SRC, 600 * HZ_PER_MHZ },
496+
{ IMX8MP_CLK_HSIO_AXI, 400 * HZ_PER_MHZ },
497+
{ IMX8MP_CLK_MEDIA_ISP, 400 * HZ_PER_MHZ },
498+
{ IMX8MP_CLK_VPU_BUS, 600 * HZ_PER_MHZ },
499+
{ IMX8MP_CLK_MEDIA_AXI, 400 * HZ_PER_MHZ },
500+
{ IMX8MP_CLK_HDMI_AXI, 400 * HZ_PER_MHZ },
501+
{ IMX8MP_CLK_GPU_AXI, 600 * HZ_PER_MHZ },
502+
{ IMX8MP_CLK_GPU_AHB, 300 * HZ_PER_MHZ },
503+
{ IMX8MP_CLK_NOC, 800 * HZ_PER_MHZ },
504+
{ IMX8MP_CLK_NOC_IO, 600 * HZ_PER_MHZ },
505+
{ IMX8MP_CLK_ML_AHB, 300 * HZ_PER_MHZ },
506+
{ IMX8MP_CLK_VPU_G1, 600 * HZ_PER_MHZ },
507+
{ IMX8MP_CLK_VPU_G2, 500 * HZ_PER_MHZ },
508+
{ IMX8MP_CLK_MEDIA_CAM1_PIX, 400 * HZ_PER_MHZ },
509+
{ IMX8MP_CLK_VPU_VC8000E, 400 * HZ_PER_MHZ }, /* Datasheet claims 500MHz */
510+
{ IMX8MP_CLK_DRAM_CORE, 800 * HZ_PER_MHZ },
511+
{ IMX8MP_CLK_GIC, 400 * HZ_PER_MHZ },
512+
{ /* Sentinel */ }
513+
};
514+
515+
static const struct imx8mp_clock_constraints imx8mp_clock_overdrive_constraints[] = {
516+
{ IMX8MP_CLK_M7_CORE, 800 * HZ_PER_MHZ},
517+
{ IMX8MP_CLK_ML_CORE, 1000 * HZ_PER_MHZ },
518+
{ IMX8MP_CLK_GPU3D_CORE, 1000 * HZ_PER_MHZ },
519+
{ IMX8MP_CLK_GPU3D_SHADER_CORE, 1000 * HZ_PER_MHZ },
520+
{ IMX8MP_CLK_GPU2D_CORE, 1000 * HZ_PER_MHZ },
521+
{ IMX8MP_CLK_AUDIO_AXI_SRC, 800 * HZ_PER_MHZ },
522+
{ IMX8MP_CLK_HSIO_AXI, 500 * HZ_PER_MHZ },
523+
{ IMX8MP_CLK_MEDIA_ISP, 500 * HZ_PER_MHZ },
524+
{ IMX8MP_CLK_VPU_BUS, 800 * HZ_PER_MHZ },
525+
{ IMX8MP_CLK_MEDIA_AXI, 500 * HZ_PER_MHZ },
526+
{ IMX8MP_CLK_HDMI_AXI, 500 * HZ_PER_MHZ },
527+
{ IMX8MP_CLK_GPU_AXI, 800 * HZ_PER_MHZ },
528+
{ IMX8MP_CLK_GPU_AHB, 400 * HZ_PER_MHZ },
529+
{ IMX8MP_CLK_NOC, 1000 * HZ_PER_MHZ },
530+
{ IMX8MP_CLK_NOC_IO, 800 * HZ_PER_MHZ },
531+
{ IMX8MP_CLK_ML_AHB, 400 * HZ_PER_MHZ },
532+
{ IMX8MP_CLK_VPU_G1, 800 * HZ_PER_MHZ },
533+
{ IMX8MP_CLK_VPU_G2, 700 * HZ_PER_MHZ },
534+
{ IMX8MP_CLK_MEDIA_CAM1_PIX, 500 * HZ_PER_MHZ },
535+
{ IMX8MP_CLK_VPU_VC8000E, 500 * HZ_PER_MHZ }, /* Datasheet claims 400MHz */
536+
{ IMX8MP_CLK_DRAM_CORE, 1000 * HZ_PER_MHZ },
537+
{ IMX8MP_CLK_GIC, 500 * HZ_PER_MHZ },
538+
{ /* Sentinel */ }
539+
};
540+
541+
static void imx8mp_clocks_apply_constraints(const struct imx8mp_clock_constraints constraints[])
542+
{
543+
const struct imx8mp_clock_constraints *constr;
544+
545+
for (constr = constraints; constr->clkid; constr++)
546+
clk_hw_set_rate_range(hws[constr->clkid], 0, constr->maxrate);
547+
}
548+
409549
static int imx8mp_clocks_probe(struct platform_device *pdev)
410550
{
411551
struct device *dev = &pdev->dev;
412552
struct device_node *np;
413553
void __iomem *anatop_base, *ccm_base;
554+
const char *opmode;
414555
int err;
415556

416557
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop");
@@ -715,6 +856,16 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
715856

716857
imx_check_clk_hws(hws, IMX8MP_CLK_END);
717858

859+
imx8mp_clocks_apply_constraints(imx8mp_clock_common_constraints);
860+
861+
err = of_property_read_string(np, "fsl,operating-mode", &opmode);
862+
if (!err) {
863+
if (!strcmp(opmode, "nominal"))
864+
imx8mp_clocks_apply_constraints(imx8mp_clock_nominal_constraints);
865+
else if (!strcmp(opmode, "overdrive"))
866+
imx8mp_clocks_apply_constraints(imx8mp_clock_overdrive_constraints);
867+
}
868+
718869
err = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
719870
if (err < 0) {
720871
dev_err(dev, "failed to register hws for i.MX8MP\n");

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