@@ -1276,23 +1276,12 @@ int sdw_configure_dpn_intr(struct sdw_slave *slave,
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return ret ;
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}
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- static int sdw_slave_set_frequency (struct sdw_slave * slave )
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+ int sdw_slave_get_scale_index (struct sdw_slave * slave , u8 * base )
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{
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u32 mclk_freq = slave -> bus -> prop .mclk_freq ;
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u32 curr_freq = slave -> bus -> params .curr_dr_freq >> 1 ;
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unsigned int scale ;
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u8 scale_index ;
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- u8 base ;
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- int ret ;
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-
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- /*
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- * frequency base and scale registers are required for SDCA
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- * devices. They may also be used for 1.2+/non-SDCA devices.
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- * Driver can set the property, we will need a DisCo property
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- * to discover this case from platform firmware.
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- */
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- if (!slave -> id .class_id && !slave -> prop .clock_reg_supported )
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- return 0 ;
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if (!mclk_freq ) {
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dev_err (& slave -> dev ,
@@ -1311,19 +1300,19 @@ static int sdw_slave_set_frequency(struct sdw_slave *slave)
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*/
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if (!(19200000 % mclk_freq )) {
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mclk_freq = 19200000 ;
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- base = SDW_SCP_BASE_CLOCK_19200000_HZ ;
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+ * base = SDW_SCP_BASE_CLOCK_19200000_HZ ;
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} else if (!(22579200 % mclk_freq )) {
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mclk_freq = 22579200 ;
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- base = SDW_SCP_BASE_CLOCK_22579200_HZ ;
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+ * base = SDW_SCP_BASE_CLOCK_22579200_HZ ;
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} else if (!(24576000 % mclk_freq )) {
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mclk_freq = 24576000 ;
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- base = SDW_SCP_BASE_CLOCK_24576000_HZ ;
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+ * base = SDW_SCP_BASE_CLOCK_24576000_HZ ;
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} else if (!(32000000 % mclk_freq )) {
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mclk_freq = 32000000 ;
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- base = SDW_SCP_BASE_CLOCK_32000000_HZ ;
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+ * base = SDW_SCP_BASE_CLOCK_32000000_HZ ;
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} else if (!(96000000 % mclk_freq )) {
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mclk_freq = 24000000 ;
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- base = SDW_SCP_BASE_CLOCK_24000000_HZ ;
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+ * base = SDW_SCP_BASE_CLOCK_24000000_HZ ;
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} else {
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dev_err (& slave -> dev ,
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"Unsupported clock base, mclk %d\n" ,
@@ -1354,6 +1343,34 @@ static int sdw_slave_set_frequency(struct sdw_slave *slave)
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}
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scale_index ++ ;
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+ dev_dbg (& slave -> dev ,
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+ "Configured bus base %d, scale %d, mclk %d, curr_freq %d\n" ,
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+ * base , scale_index , mclk_freq , curr_freq );
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+
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+ return scale_index ;
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+ }
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+ EXPORT_SYMBOL (sdw_slave_get_scale_index );
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+
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+ static int sdw_slave_set_frequency (struct sdw_slave * slave )
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+ {
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+ int scale_index ;
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+ u8 base ;
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+ int ret ;
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+
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+ /*
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+ * frequency base and scale registers are required for SDCA
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+ * devices. They may also be used for 1.2+/non-SDCA devices.
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+ * Driver can set the property directly, for now there's no
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+ * DisCo property to discover support for the scaling registers
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+ * from platform firmware.
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+ */
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+ if (!slave -> id .class_id && !slave -> prop .clock_reg_supported )
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+ return 0 ;
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+
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+ scale_index = sdw_slave_get_scale_index (slave , & base );
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+ if (scale_index < 0 )
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+ return scale_index ;
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+
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ret = sdw_write_no_pm (slave , SDW_SCP_BUS_CLOCK_BASE , base );
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if (ret < 0 ) {
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dev_err (& slave -> dev ,
@@ -1373,10 +1390,6 @@ static int sdw_slave_set_frequency(struct sdw_slave *slave)
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dev_err (& slave -> dev ,
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"SDW_SCP_BUSCLOCK_SCALE_B1 write failed:%d\n" , ret );
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- dev_dbg (& slave -> dev ,
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- "Configured bus base %d, scale %d, mclk %d, curr_freq %d\n" ,
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- base , scale_index , mclk_freq , curr_freq );
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-
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return ret ;
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}
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