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broonie
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kselftest/arm64: Add 2024 dpISA extensions to hwcap test
Add coverage of the hwcaps for the 2024 dpISA extensions to the hwcap test. We don't actually test SIGILL generation for CMPBR since the need to branch makes it a pain to generate and the SIGILL detection would be unreliable anyway. Since this should be very unusual we provide a stub function rather than supporting a missing test. The sigill functions aren't well sorted in the file so the ordering is a bit random. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20250107-arm64-2024-dpisa-v5-5-7578da51fc3d@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
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  • tools/testing/selftests/arm64/abi

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‎tools/testing/selftests/arm64/abi/hwcap.c

Lines changed: 233 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,12 @@ static void atomics_sigill(void)
4646
asm volatile(".inst 0xb82003ff" : : : );
4747
}
4848

49+
static void cmpbr_sigill(void)
50+
{
51+
/* Not implemented, too complicated and unreliable anyway */
52+
}
53+
54+
4955
static void crc32_sigill(void)
5056
{
5157
/* CRC32W W0, W0, W1 */
@@ -82,6 +88,18 @@ static void f8fma_sigill(void)
8288
asm volatile(".inst 0xec0fc00");
8389
}
8490

91+
static void f8mm4_sigill(void)
92+
{
93+
/* FMMLA V0.4SH, V0.16B, V0.16B */
94+
asm volatile(".inst 0x6e00ec00");
95+
}
96+
97+
static void f8mm8_sigill(void)
98+
{
99+
/* FMMLA V0.4S, V0.16B, V0.16B */
100+
asm volatile(".inst 0x6e80ec00");
101+
}
102+
85103
static void faminmax_sigill(void)
86104
{
87105
/* FAMIN V0.4H, V0.4H, V0.4H */
@@ -98,6 +116,12 @@ static void fpmr_sigill(void)
98116
asm volatile("mrs x0, S3_3_C4_C4_2" : : : "x0");
99117
}
100118

119+
static void fprcvt_sigill(void)
120+
{
121+
/* FCVTAS S0, H0 */
122+
asm volatile(".inst 0x1efa0000");
123+
}
124+
101125
static void gcs_sigill(void)
102126
{
103127
unsigned long *gcspr;
@@ -226,6 +250,42 @@ static void sme2p1_sigill(void)
226250
asm volatile("msr S0_3_C4_C6_3, xzr" : : : );
227251
}
228252

253+
static void sme2p2_sigill(void)
254+
{
255+
/* SMSTART SM */
256+
asm volatile("msr S0_3_C4_C3_3, xzr" : : : );
257+
258+
/* UXTB Z0.D, P0/Z, Z0.D */
259+
asm volatile(".inst 0x4c1a000" : : : );
260+
261+
/* SMSTOP */
262+
asm volatile("msr S0_3_C4_C6_3, xzr" : : : );
263+
}
264+
265+
static void sme_aes_sigill(void)
266+
{
267+
/* SMSTART SM */
268+
asm volatile("msr S0_3_C4_C3_3, xzr" : : : );
269+
270+
/* AESD z0.b, z0.b, z0.b */
271+
asm volatile(".inst 0x4522e400" : : : "z0");
272+
273+
/* SMSTOP */
274+
asm volatile("msr S0_3_C4_C6_3, xzr" : : : );
275+
}
276+
277+
static void sme_sbitperm_sigill(void)
278+
{
279+
/* SMSTART SM */
280+
asm volatile("msr S0_3_C4_C3_3, xzr" : : : );
281+
282+
/* BDEP Z0.B, Z0.B, Z0.B */
283+
asm volatile(".inst 0x4500b400" : : : "z0");
284+
285+
/* SMSTOP */
286+
asm volatile("msr S0_3_C4_C6_3, xzr" : : : );
287+
}
288+
229289
static void smei16i32_sigill(void)
230290
{
231291
/* SMSTART */
@@ -339,8 +399,44 @@ static void smesf8fma_sigill(void)
339399
/* SMSTART */
340400
asm volatile("msr S0_3_C4_C7_3, xzr" : : : );
341401

342-
/* FMLALB V0.8H, V0.16B, V0.16B */
343-
asm volatile(".inst 0xec0fc00");
402+
/* FMLALB Z0.8H, Z0.B, Z0.B */
403+
asm volatile(".inst 0x64205000");
404+
405+
/* SMSTOP */
406+
asm volatile("msr S0_3_C4_C6_3, xzr" : : : );
407+
}
408+
409+
static void smesfexpa_sigill(void)
410+
{
411+
/* SMSTART */
412+
asm volatile("msr S0_3_C4_C7_3, xzr" : : : );
413+
414+
/* FEXPA Z0.D, Z0.D */
415+
asm volatile(".inst 0x04e0b800");
416+
417+
/* SMSTOP */
418+
asm volatile("msr S0_3_C4_C6_3, xzr" : : : );
419+
}
420+
421+
static void smesmop4_sigill(void)
422+
{
423+
/* SMSTART */
424+
asm volatile("msr S0_3_C4_C7_3, xzr" : : : );
425+
426+
/* SMOP4A ZA0.S, Z0.B, { Z0.B - Z1.B } */
427+
asm volatile(".inst 0x80108000");
428+
429+
/* SMSTOP */
430+
asm volatile("msr S0_3_C4_C6_3, xzr" : : : );
431+
}
432+
433+
static void smestmop_sigill(void)
434+
{
435+
/* SMSTART */
436+
asm volatile("msr S0_3_C4_C7_3, xzr" : : : );
437+
438+
/* STMOPA ZA0.S, { Z0.H - Z1.H }, Z0.H, Z20[0] */
439+
asm volatile(".inst 0x80408008");
344440

345441
/* SMSTOP */
346442
asm volatile("msr S0_3_C4_C6_3, xzr" : : : );
@@ -364,18 +460,42 @@ static void sve2p1_sigill(void)
364460
asm volatile(".inst 0x65000000" : : : "z0");
365461
}
366462

463+
static void sve2p2_sigill(void)
464+
{
465+
/* NOT Z0.D, P0/Z, Z0.D */
466+
asm volatile(".inst 0x4cea000" : : : "z0");
467+
}
468+
367469
static void sveaes_sigill(void)
368470
{
369471
/* AESD z0.b, z0.b, z0.b */
370472
asm volatile(".inst 0x4522e400" : : : "z0");
371473
}
372474

475+
static void sveaes2_sigill(void)
476+
{
477+
/* AESD {Z0.B - Z1.B }, { Z0.B - Z1.B }, Z0.Q */
478+
asm volatile(".inst 0x4522ec00" : : : "z0");
479+
}
480+
373481
static void sveb16b16_sigill(void)
374482
{
375483
/* BFADD Z0.H, Z0.H, Z0.H */
376484
asm volatile(".inst 0x65000000" : : : );
377485
}
378486

487+
static void svebfscale_sigill(void)
488+
{
489+
/* BFSCALE Z0.H, P0/M, Z0.H, Z0.H */
490+
asm volatile(".inst 0x65098000" : : : "z0");
491+
}
492+
493+
static void svef16mm_sigill(void)
494+
{
495+
/* FMMLA Z0.S, Z0.H, Z0.H */
496+
asm volatile(".inst 0x6420e400");
497+
}
498+
379499
static void svepmull_sigill(void)
380500
{
381501
/* PMULLB Z0.Q, Z0.D, Z0.D */
@@ -394,6 +514,12 @@ static void svesha3_sigill(void)
394514
asm volatile(".inst 0x4203800" : : : "z0");
395515
}
396516

517+
static void sveeltperm_sigill(void)
518+
{
519+
/* COMPACT Z0.B, P0, Z0.B */
520+
asm volatile(".inst 0x5218000" : : : "x0");
521+
}
522+
397523
static void svesm4_sigill(void)
398524
{
399525
/* SM4E Z0.S, Z0.S, Z0.S */
@@ -469,6 +595,13 @@ static const struct hwcap_data {
469595
.cpuinfo = "aes",
470596
.sigill_fn = aes_sigill,
471597
},
598+
{
599+
.name = "CMPBR",
600+
.at_hwcap = AT_HWCAP,
601+
.hwcap_bit = HWCAP_CMPBR,
602+
.cpuinfo = "cmpbr",
603+
.sigill_fn = cmpbr_sigill,
604+
},
472605
{
473606
.name = "CRC32",
474607
.at_hwcap = AT_HWCAP,
@@ -523,6 +656,20 @@ static const struct hwcap_data {
523656
.cpuinfo = "f8fma",
524657
.sigill_fn = f8fma_sigill,
525658
},
659+
{
660+
.name = "F8MM8",
661+
.at_hwcap = AT_HWCAP,
662+
.hwcap_bit = HWCAP_F8MM8,
663+
.cpuinfo = "f8mm8",
664+
.sigill_fn = f8mm8_sigill,
665+
},
666+
{
667+
.name = "F8MM4",
668+
.at_hwcap = AT_HWCAP,
669+
.hwcap_bit = HWCAP_F8MM4,
670+
.cpuinfo = "f8mm4",
671+
.sigill_fn = f8mm4_sigill,
672+
},
526673
{
527674
.name = "FAMINMAX",
528675
.at_hwcap = AT_HWCAP2,
@@ -545,6 +692,13 @@ static const struct hwcap_data {
545692
.sigill_fn = fpmr_sigill,
546693
.sigill_reliable = true,
547694
},
695+
{
696+
.name = "FPRCVT",
697+
.at_hwcap = AT_HWCAP,
698+
.hwcap_bit = HWCAP_FPRCVT,
699+
.cpuinfo = "fprcvt",
700+
.sigill_fn = fprcvt_sigill,
701+
},
548702
{
549703
.name = "GCS",
550704
.at_hwcap = AT_HWCAP,
@@ -691,6 +845,20 @@ static const struct hwcap_data {
691845
.cpuinfo = "sme2p1",
692846
.sigill_fn = sme2p1_sigill,
693847
},
848+
{
849+
.name = "SME 2.2",
850+
.at_hwcap = AT_HWCAP,
851+
.hwcap_bit = HWCAP_SME2P2,
852+
.cpuinfo = "sme2p2",
853+
.sigill_fn = sme2p2_sigill,
854+
},
855+
{
856+
.name = "SME AES",
857+
.at_hwcap = AT_HWCAP,
858+
.hwcap_bit = HWCAP_SME_AES,
859+
.cpuinfo = "smeaes",
860+
.sigill_fn = sme_aes_sigill,
861+
},
694862
{
695863
.name = "SME I16I32",
696864
.at_hwcap = AT_HWCAP2,
@@ -740,6 +908,13 @@ static const struct hwcap_data {
740908
.cpuinfo = "smelutv2",
741909
.sigill_fn = smelutv2_sigill,
742910
},
911+
{
912+
.name = "SME SBITPERM",
913+
.at_hwcap = AT_HWCAP,
914+
.hwcap_bit = HWCAP_SME_SBITPERM,
915+
.cpuinfo = "smesbitperm",
916+
.sigill_fn = sme_sbitperm_sigill,
917+
},
743918
{
744919
.name = "SME SF8FMA",
745920
.at_hwcap = AT_HWCAP2,
@@ -761,6 +936,27 @@ static const struct hwcap_data {
761936
.cpuinfo = "smesf8dp4",
762937
.sigill_fn = smesf8dp4_sigill,
763938
},
939+
{
940+
.name = "SME SFEXPA",
941+
.at_hwcap = AT_HWCAP,
942+
.hwcap_bit = HWCAP_SME_SFEXPA,
943+
.cpuinfo = "smesfexpa",
944+
.sigill_fn = smesfexpa_sigill,
945+
},
946+
{
947+
.name = "SME SMOP4",
948+
.at_hwcap = AT_HWCAP,
949+
.hwcap_bit = HWCAP_SME_SMOP4,
950+
.cpuinfo = "smesmop4",
951+
.sigill_fn = smesmop4_sigill,
952+
},
953+
{
954+
.name = "SME STMOP",
955+
.at_hwcap = AT_HWCAP,
956+
.hwcap_bit = HWCAP_SME_STMOP,
957+
.cpuinfo = "smestmop",
958+
.sigill_fn = smestmop_sigill,
959+
},
764960
{
765961
.name = "SVE",
766962
.at_hwcap = AT_HWCAP,
@@ -783,13 +979,48 @@ static const struct hwcap_data {
783979
.cpuinfo = "sve2p1",
784980
.sigill_fn = sve2p1_sigill,
785981
},
982+
{
983+
.name = "SVE 2.2",
984+
.at_hwcap = AT_HWCAP,
985+
.hwcap_bit = HWCAP_SVE2P2,
986+
.cpuinfo = "sve2p2",
987+
.sigill_fn = sve2p2_sigill,
988+
},
786989
{
787990
.name = "SVE AES",
788991
.at_hwcap = AT_HWCAP2,
789992
.hwcap_bit = HWCAP2_SVEAES,
790993
.cpuinfo = "sveaes",
791994
.sigill_fn = sveaes_sigill,
792995
},
996+
{
997+
.name = "SVE AES2",
998+
.at_hwcap = AT_HWCAP,
999+
.hwcap_bit = HWCAP_SVE_AES2,
1000+
.cpuinfo = "sveaes2",
1001+
.sigill_fn = sveaes2_sigill,
1002+
},
1003+
{
1004+
.name = "SVE BFSCALE",
1005+
.at_hwcap = AT_HWCAP,
1006+
.hwcap_bit = HWCAP_SVE_BFSCALE,
1007+
.cpuinfo = "svebfscale",
1008+
.sigill_fn = svebfscale_sigill,
1009+
},
1010+
{
1011+
.name = "SVE ELTPERM",
1012+
.at_hwcap = AT_HWCAP,
1013+
.hwcap_bit = HWCAP_SVE_ELTPERM,
1014+
.cpuinfo = "sveeltperm",
1015+
.sigill_fn = sveeltperm_sigill,
1016+
},
1017+
{
1018+
.name = "SVE F16MM",
1019+
.at_hwcap = AT_HWCAP,
1020+
.hwcap_bit = HWCAP_SVE_F16MM,
1021+
.cpuinfo = "svef16mm",
1022+
.sigill_fn = svef16mm_sigill,
1023+
},
7931024
{
7941025
.name = "SVE2 B16B16",
7951026
.at_hwcap = AT_HWCAP2,

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