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amitdanielkachhapctmarinas
amitdanielkachhap
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ctmarinas
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arm64: cpufeature: Fix the visibility of compat hwcaps
Commit 237405e ("arm64: cpufeature: Force HWCAP to be based on the sysreg visible to user-space") forced the hwcaps to use sanitised user-space view of the id registers. However, the ID register structures used to select few compat cpufeatures (vfp, crc32, ...) are masked and hence such hwcaps do not appear in /proc/cpuinfo anymore for PER_LINUX32 personality. Add the ID register structures explicitly and set the relevant entry as visible. As these ID registers are now of type visible so make them available in 64-bit userspace by making necessary changes in register emulation logic and documentation. While at it, update the comment for structure ftr_generic_32bits[] which lists the ID register that use it. Fixes: 237405e ("arm64: cpufeature: Force HWCAP to be based on the sysreg visible to user-space") Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: James Morse <james.morse@arm.com> Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com> Link: https://lore.kernel.org/r/20221103082232.19189-1-amit.kachhap@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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‎Documentation/arm64/cpu-feature-registers.rst

Lines changed: 37 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -92,7 +92,7 @@ operation if the source belongs to the supported system register space.
9292

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The infrastructure emulates only the following system register space::
9494

95-
Op0=3, Op1=0, CRn=0, CRm=0,4,5,6,7
95+
Op0=3, Op1=0, CRn=0, CRm=0,2,3,4,5,6,7
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(See Table C5-6 'System instruction encodings for non-Debug System
9898
register accesses' in ARMv8 ARM DDI 0487A.h, for the list of
@@ -293,6 +293,42 @@ infrastructure:
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| WFXT | [3-0] | y |
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+------------------------------+---------+---------+
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296+
10) MVFR0_EL1 - AArch32 Media and VFP Feature Register 0
297+
298+
+------------------------------+---------+---------+
299+
| Name | bits | visible |
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+------------------------------+---------+---------+
301+
| FPDP | [11-8] | y |
302+
+------------------------------+---------+---------+
303+
304+
11) MVFR1_EL1 - AArch32 Media and VFP Feature Register 1
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+------------------------------+---------+---------+
307+
| Name | bits | visible |
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+------------------------------+---------+---------+
309+
| SIMDFMAC | [31-28] | y |
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+------------------------------+---------+---------+
311+
| SIMDSP | [19-16] | y |
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+------------------------------+---------+---------+
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| SIMDInt | [15-12] | y |
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+------------------------------+---------+---------+
315+
| SIMDLS | [11-8] | y |
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+------------------------------+---------+---------+
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318+
12) ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5
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+------------------------------+---------+---------+
321+
| Name | bits | visible |
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+------------------------------+---------+---------+
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| CRC32 | [19-16] | y |
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+------------------------------+---------+---------+
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| SHA2 | [15-12] | y |
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+------------------------------+---------+---------+
327+
| SHA1 | [11-8] | y |
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+------------------------------+---------+---------+
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| AES | [7-4] | y |
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+------------------------------+---------+---------+
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296332

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Appendix I: Example
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-------------------

‎arch/arm64/kernel/cpufeature.c

Lines changed: 33 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -428,6 +428,30 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
428428
ARM64_FTR_END,
429429
};
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431+
static const struct arm64_ftr_bits ftr_mvfr0[] = {
432+
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPROUND_SHIFT, 4, 0),
433+
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSHVEC_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSQRT_SHIFT, 4, 0),
435+
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPDIVIDE_SHIFT, 4, 0),
436+
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPTRAP_SHIFT, 4, 0),
437+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPDP_SHIFT, 4, 0),
438+
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSP_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_SIMD_SHIFT, 4, 0),
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ARM64_FTR_END,
441+
};
442+
443+
static const struct arm64_ftr_bits ftr_mvfr1[] = {
444+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDFMAC_SHIFT, 4, 0),
445+
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPHP_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDHP_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDSP_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDINT_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDLS_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPDNAN_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPFTZ_SHIFT, 4, 0),
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ARM64_FTR_END,
453+
};
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431455
static const struct arm64_ftr_bits ftr_mvfr2[] = {
432456
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0),
433457
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0),
@@ -458,10 +482,10 @@ static const struct arm64_ftr_bits ftr_id_isar0[] = {
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459483
static const struct arm64_ftr_bits ftr_id_isar5[] = {
460484
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
461-
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
462-
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
463-
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
464-
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
485+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
486+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
487+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
488+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
465489
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
466490
ARM64_FTR_END,
467491
};
@@ -574,7 +598,7 @@ static const struct arm64_ftr_bits ftr_smcr[] = {
574598
* Common ftr bits for a 32bit register with all hidden, strict
575599
* attributes, with 4bit feature fields and a default safe value of
576600
* 0. Covers the following 32bit registers:
577-
* id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
601+
* id_isar[1-3], id_mmfr[1-3]
578602
*/
579603
static const struct arm64_ftr_bits ftr_generic_32bits[] = {
580604
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
@@ -645,8 +669,8 @@ static const struct __ftr_reg_entry {
645669
ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
646670

647671
/* Op1 = 0, CRn = 0, CRm = 3 */
648-
ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
649-
ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
672+
ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0),
673+
ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1),
650674
ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
651675
ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
652676
ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
@@ -3339,7 +3363,7 @@ static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *c
33393363

33403364
/*
33413365
* We emulate only the following system register space.
3342-
* Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
3366+
* Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7]
33433367
* See Table C5-6 System instruction encodings for System register accesses,
33443368
* ARMv8 ARM(ARM DDI 0487A.f) for more details.
33453369
*/
@@ -3349,7 +3373,7 @@ static inline bool __attribute_const__ is_emulated(u32 id)
33493373
sys_reg_CRn(id) == 0x0 &&
33503374
sys_reg_Op1(id) == 0x0 &&
33513375
(sys_reg_CRm(id) == 0 ||
3352-
((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
3376+
((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7))));
33533377
}
33543378

33553379
/*

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