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jwrdegoedegregkh
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serial: 8250_dw: Revert: Do not reclock if already at correct rate
Commit e5d6bd2 ("serial: 8250_dw: Do not reclock if already at correct rate") breaks the dw UARTs on Intel Bay Trail (BYT) and Cherry Trail (CHT) SoCs. Before this change the RTL8732BS Bluetooth HCI which is found connected over the dw UART on both BYT and CHT boards works properly: Bluetooth: hci0: RTL: examining hci_ver=06 hci_rev=000b lmp_ver=06 lmp_subver=8723 Bluetooth: hci0: RTL: rom_version status=0 version=1 Bluetooth: hci0: RTL: loading rtl_bt/rtl8723bs_fw.bin Bluetooth: hci0: RTL: loading rtl_bt/rtl8723bs_config-OBDA8723.bin Bluetooth: hci0: RTL: cfg_sz 64, total sz 24508 Bluetooth: hci0: RTL: fw version 0x365d462e where as after this change probing it fails: Bluetooth: hci0: RTL: examining hci_ver=06 hci_rev=000b lmp_ver=06 lmp_subver=8723 Bluetooth: hci0: RTL: rom_version status=0 version=1 Bluetooth: hci0: RTL: loading rtl_bt/rtl8723bs_fw.bin Bluetooth: hci0: RTL: loading rtl_bt/rtl8723bs_config-OBDA8723.bin Bluetooth: hci0: RTL: cfg_sz 64, total sz 24508 Bluetooth: hci0: command 0xfc20 tx timeout Bluetooth: hci0: RTL: download fw command failed (-110) Revert the changes to fix this regression. Fixes: e5d6bd2 ("serial: 8250_dw: Do not reclock if already at correct rate") Cc: stable@vger.kernel.org Cc: Peter Collingbourne <pcc@google.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Peter Collingbourne <pcc@google.com> Link: https://lore.kernel.org/r/20240317214123.34482-1-hdegoede@redhat.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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drivers/tty/serial/8250/8250_dw.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -356,18 +356,18 @@ static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
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long rate;
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int ret;
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359+
clk_disable_unprepare(d->clk);
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rate = clk_round_rate(d->clk, newrate);
360-
if (rate > 0 && p->uartclk != rate) {
361-
clk_disable_unprepare(d->clk);
361+
if (rate > 0) {
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/*
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* Note that any clock-notifer worker will block in
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* serial8250_update_uartclk() until we are done.
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*/
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ret = clk_set_rate(d->clk, newrate);
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if (!ret)
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p->uartclk = rate;
369-
clk_prepare_enable(d->clk);
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}
370+
clk_prepare_enable(d->clk);
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dw8250_do_set_termios(p, termios, old);
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}

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