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ambaruskrzk
ambarus
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krzk
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clk: samsung: gs101: propagate PERIC1 USI SPI clock rate
When SPI transfer is being prepared, the spi-s3c64xx driver will call clk_set_rate() to change the rate of SPI source clock (IPCLK). But IPCLK is a gate (leaf) clock, so it must propagate the rate change up the clock tree, so that corresponding MUX/DIV clocks can actually change their values. Add CLK_SET_RATE_PARENT flag to corresponding clocks for all USI instances in GS101 PERIC1: USI{0, 9, 10, 11, 12, 13}. This change involves the following clocks: PERIC1 USI*: Clock Div range MUX Selection ------------------------------------------------------------------- gout_peric1_peric1_top0_ipclk_* - - dout_peric1_usi*_usi /1..16 - mout_peric1_usi*_usi_user - {24.5 MHz, 400 MHz} With input clock of 400 MHz this scheme provides the following IPCLK rate range, for each USI block: PERIC1 USI*: 1.5 MHz ... 400 MHz Accounting for internal /4 divider in SPI blocks, and because the max SPI frequency is limited at 50 MHz, it gives us next SPI SCK rates: PERIC1 USI_SPI*: 384 KHz ... 49.9 MHz Which shall be fine for the applications of the SPI bus. Note that with this we allow the reparenting of the MUX_USIx clocks to OSCCLK. Each instance of the USI IP has its own MUX_USI clock, thus the reparenting of a MUX_USI clock corresponds to a single instance of the USI IP. The datasheet mentions OSCCLK just in the low-power mode context, but the downstream driver reparents too the MUX_USI clocks to OSCCLK. Follow the downstream driver and do the same. Fixes: 2999e78 ("clk: samsung: gs101: add support for cmu_peric1") Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: André Draszik <andre.draszik@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240419100915.2168573-3-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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‎drivers/clk/samsung/clk-gs101.c

Lines changed: 48 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -3239,47 +3239,53 @@ static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
32393239
MUX(CLK_MOUT_PERIC1_I3C_USER,
32403240
"mout_peric1_i3c_user", mout_peric1_nonbususer_p,
32413241
PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, 4, 1),
3242-
MUX(CLK_MOUT_PERIC1_USI0_USI_USER,
3243-
"mout_peric1_usi0_usi_user", mout_peric1_nonbususer_p,
3244-
PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 4, 1),
3245-
MUX(CLK_MOUT_PERIC1_USI10_USI_USER,
3246-
"mout_peric1_usi10_usi_user", mout_peric1_nonbususer_p,
3247-
PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4, 1),
3248-
MUX(CLK_MOUT_PERIC1_USI11_USI_USER,
3249-
"mout_peric1_usi11_usi_user", mout_peric1_nonbususer_p,
3250-
PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4, 1),
3251-
MUX(CLK_MOUT_PERIC1_USI12_USI_USER,
3252-
"mout_peric1_usi12_usi_user", mout_peric1_nonbususer_p,
3253-
PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4, 1),
3254-
MUX(CLK_MOUT_PERIC1_USI13_USI_USER,
3255-
"mout_peric1_usi13_usi_user", mout_peric1_nonbususer_p,
3256-
PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 4, 1),
3257-
MUX(CLK_MOUT_PERIC1_USI9_USI_USER,
3258-
"mout_peric1_usi9_usi_user", mout_peric1_nonbususer_p,
3259-
PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 4, 1),
3242+
nMUX(CLK_MOUT_PERIC1_USI0_USI_USER,
3243+
"mout_peric1_usi0_usi_user", mout_peric1_nonbususer_p,
3244+
PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 4, 1),
3245+
nMUX(CLK_MOUT_PERIC1_USI10_USI_USER,
3246+
"mout_peric1_usi10_usi_user", mout_peric1_nonbususer_p,
3247+
PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4, 1),
3248+
nMUX(CLK_MOUT_PERIC1_USI11_USI_USER,
3249+
"mout_peric1_usi11_usi_user", mout_peric1_nonbususer_p,
3250+
PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4, 1),
3251+
nMUX(CLK_MOUT_PERIC1_USI12_USI_USER,
3252+
"mout_peric1_usi12_usi_user", mout_peric1_nonbususer_p,
3253+
PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4, 1),
3254+
nMUX(CLK_MOUT_PERIC1_USI13_USI_USER,
3255+
"mout_peric1_usi13_usi_user", mout_peric1_nonbususer_p,
3256+
PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 4, 1),
3257+
nMUX(CLK_MOUT_PERIC1_USI9_USI_USER,
3258+
"mout_peric1_usi9_usi_user", mout_peric1_nonbususer_p,
3259+
PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 4, 1),
32603260
};
32613261

32623262
static const struct samsung_div_clock peric1_div_clks[] __initconst = {
32633263
DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c", "mout_peric1_i3c_user",
32643264
CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4),
3265-
DIV(CLK_DOUT_PERIC1_USI0_USI,
3266-
"dout_peric1_usi0_usi", "mout_peric1_usi0_usi_user",
3267-
CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 0, 4),
3268-
DIV(CLK_DOUT_PERIC1_USI10_USI,
3269-
"dout_peric1_usi10_usi", "mout_peric1_usi10_usi_user",
3270-
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4),
3271-
DIV(CLK_DOUT_PERIC1_USI11_USI,
3272-
"dout_peric1_usi11_usi", "mout_peric1_usi11_usi_user",
3273-
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4),
3274-
DIV(CLK_DOUT_PERIC1_USI12_USI,
3275-
"dout_peric1_usi12_usi", "mout_peric1_usi12_usi_user",
3276-
CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4),
3277-
DIV(CLK_DOUT_PERIC1_USI13_USI,
3278-
"dout_peric1_usi13_usi", "mout_peric1_usi13_usi_user",
3279-
CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 0, 4),
3280-
DIV(CLK_DOUT_PERIC1_USI9_USI,
3281-
"dout_peric1_usi9_usi", "mout_peric1_usi9_usi_user",
3282-
CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 0, 4),
3265+
DIV_F(CLK_DOUT_PERIC1_USI0_USI,
3266+
"dout_peric1_usi0_usi", "mout_peric1_usi0_usi_user",
3267+
CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 0, 4,
3268+
CLK_SET_RATE_PARENT, 0),
3269+
DIV_F(CLK_DOUT_PERIC1_USI10_USI,
3270+
"dout_peric1_usi10_usi", "mout_peric1_usi10_usi_user",
3271+
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4,
3272+
CLK_SET_RATE_PARENT, 0),
3273+
DIV_F(CLK_DOUT_PERIC1_USI11_USI,
3274+
"dout_peric1_usi11_usi", "mout_peric1_usi11_usi_user",
3275+
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4,
3276+
CLK_SET_RATE_PARENT, 0),
3277+
DIV_F(CLK_DOUT_PERIC1_USI12_USI,
3278+
"dout_peric1_usi12_usi", "mout_peric1_usi12_usi_user",
3279+
CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4,
3280+
CLK_SET_RATE_PARENT, 0),
3281+
DIV_F(CLK_DOUT_PERIC1_USI13_USI,
3282+
"dout_peric1_usi13_usi", "mout_peric1_usi13_usi_user",
3283+
CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 0, 4,
3284+
CLK_SET_RATE_PARENT, 0),
3285+
DIV_F(CLK_DOUT_PERIC1_USI9_USI,
3286+
"dout_peric1_usi9_usi", "mout_peric1_usi9_usi_user",
3287+
CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 0, 4,
3288+
CLK_SET_RATE_PARENT, 0),
32833289
};
32843290

32853291
static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
@@ -3314,27 +3320,27 @@ static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
33143320
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1,
33153321
"gout_peric1_peric1_top0_ipclk_1", "dout_peric1_usi0_usi",
33163322
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
3317-
21, 0, 0),
3323+
21, CLK_SET_RATE_PARENT, 0),
33183324
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2,
33193325
"gout_peric1_peric1_top0_ipclk_2", "dout_peric1_usi9_usi",
33203326
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
3321-
21, 0, 0),
3327+
21, CLK_SET_RATE_PARENT, 0),
33223328
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3,
33233329
"gout_peric1_peric1_top0_ipclk_3", "dout_peric1_usi10_usi",
33243330
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
3325-
21, 0, 0),
3331+
21, CLK_SET_RATE_PARENT, 0),
33263332
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4,
33273333
"gout_peric1_peric1_top0_ipclk_4", "dout_peric1_usi11_usi",
33283334
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
3329-
21, 0, 0),
3335+
21, CLK_SET_RATE_PARENT, 0),
33303336
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5,
33313337
"gout_peric1_peric1_top0_ipclk_5", "dout_peric1_usi12_usi",
33323338
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
3333-
21, 0, 0),
3339+
21, CLK_SET_RATE_PARENT, 0),
33343340
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6,
33353341
"gout_peric1_peric1_top0_ipclk_6", "dout_peric1_usi13_usi",
33363342
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
3337-
21, 0, 0),
3343+
21, CLK_SET_RATE_PARENT, 0),
33383344
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8,
33393345
"gout_peric1_peric1_top0_ipclk_8", "dout_peric1_i3c",
33403346
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,

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