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Merge tag 'perf-tools-for-v5.18-2022-03-26' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux
Pull perf tools updates from Arnaldo Carvalho de Melo: "New features: perf ftrace: - Add -n/--use-nsec option to the 'latency' subcommand. Default: usecs: $ sudo perf ftrace latency -T dput -a sleep 1 # DURATION | COUNT | GRAPH | 0 - 1 us | 2098375 | ############################# | 1 - 2 us | 61 | | 2 - 4 us | 33 | | 4 - 8 us | 13 | | 8 - 16 us | 124 | | 16 - 32 us | 123 | | 32 - 64 us | 1 | | 64 - 128 us | 0 | | 128 - 256 us | 1 | | 256 - 512 us | 0 | | Better granularity with nsec: $ sudo perf ftrace latency -T dput -a -n sleep 1 # DURATION | COUNT | GRAPH | 0 - 1 us | 0 | | 1 - 2 ns | 0 | | 2 - 4 ns | 0 | | 4 - 8 ns | 0 | | 8 - 16 ns | 0 | | 16 - 32 ns | 0 | | 32 - 64 ns | 0 | | 64 - 128 ns | 1163434 | ############## | 128 - 256 ns | 914102 | ############# | 256 - 512 ns | 884 | | 512 - 1024 ns | 613 | | 1 - 2 us | 31 | | 2 - 4 us | 17 | | 4 - 8 us | 7 | | 8 - 16 us | 123 | | 16 - 32 us | 83 | | perf lock: - Add -c/--combine-locks option to merge lock instances in the same class into a single entry. # perf lock report -c Name acquired contended avg wait(ns) total wait(ns) max wait(ns) min wait(ns) rcu_read_lock 251225 0 0 0 0 0 hrtimer_bases.lock 39450 0 0 0 0 0 &sb->s_type->i_l... 10301 1 662 662 662 662 ptlock_ptr(page) 10173 2 701 1402 760 642 &(ei->i_block_re... 8732 0 0 0 0 0 &xa->xa_lock 8088 0 0 0 0 0 &base->lock 6705 0 0 0 0 0 &p->pi_lock 5549 0 0 0 0 0 &dentry->d_lockr... 5010 4 1274 5097 1844 789 &ep->lock 3958 0 0 0 0 0 - Add -F/--field option to customize the list of fields to output: $ perf lock report -F contended,wait_max -k avg_wait Name contended max wait(ns) avg wait(ns) slock-AF_INET6 1 23543 23543 &lruvec->lru_lock 5 18317 11254 slock-AF_INET6 1 10379 10379 rcu_node_1 1 2104 2104 &dentry->d_lockr... 1 1844 1844 &dentry->d_lockr... 1 1672 1672 &newf->file_lock 15 2279 1025 &dentry->d_lockr... 1 792 792 - Add --synth=no option for record, as there is no need to symbolize, lock names comes from the tracepoints. perf record: - Threaded recording, opt-in, via the new --threads command line option. - Improve AMD IBS (Instruction-Based Sampling) error handling messages. perf script: - Add 'brstackinsnlen' field (use it with -F) for branch stacks. - Output branch sample type in 'perf script'. perf report: - Add "addr_from" and "addr_to" sort dimensions. - Print branch stack entry type in 'perf report --dump-raw-trace' - Fix symbolization for chrooted workloads. Hardware tracing: Intel PT: - Add CFE (Control Flow Event) and EVD (Event Data) packets support. - Add MODE.Exec IFLAG bit support. Explanation about these features from the "Intel® 64 and IA-32 architectures software developer’s manual combined volumes: 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4" PDF at: https://cdrdv2.intel.com/v1/dl/getContent/671200 At page 3951: "32.2.4 Event Trace is a capability that exposes details about the asynchronous events, when they are generated, and when their corresponding software event handler completes execution. These include: o Interrupts, including NMI and SMI, including the interrupt vector when defined. o Faults, exceptions including the fault vector. - Page faults additionally include the page fault address, when in context. o Event handler returns, including IRET and RSM. o VM exits and VM entries.¹ - VM exits include the values written to the “exit reason” and “exit qualification” VMCS fields. INIT and SIPI events. o TSX aborts, including the abort status returned for the RTM instructions. o Shutdown. Additionally, it provides indication of the status of the Interrupt Flag (IF), to indicate when interrupts are masked" ARM CoreSight: - Use advertised caps/min_interval as default sample_period on ARM spe. - Update deduction of TRCCONFIGR register for branch broadcast on ARM's CoreSight ETM. Vendor Events (JSON): Intel: - Update events and metrics for: Alderlake, Broadwell, Broadwell DE, BroadwellX, CascadelakeX, Elkhartlake, Bonnell, Goldmont, GoldmontPlus, Westmere EP-DP, Haswell, HaswellX, Icelake, IcelakeX, Ivybridge, Ivytown, Jaketown, Knights Landing, Nehalem EP, Sandybridge, Silvermont, Skylake, Skylake Server, SkylakeX, Tigerlake, TremontX, Westmere EP-SP, and Westmere EX. ARM: - Add support for HiSilicon CPA PMU aliasing. perf stat: - Fix forked applications enablement of counters. - The 'slots' should only be printed on a different order than the one specified on the command line when 'topdown' events are present, fix it. Miscellaneous: - Sync msr-index, cpufeatures header files with the kernel sources. - Stop using some deprecated libbpf APIs in 'perf trace'. - Fix some spelling mistakes. - Refactor the maps pointers usage to pave the way for using refcount debugging. - Only offer the --tui option on perf top, report and annotate when perf was built with libslang. - Don't mention --to-ctf in 'perf data --help' when not linking with the required library, libbabeltrace. - Use ARRAY_SIZE() instead of ad hoc equivalent, spotted by array_size.cocci. - Enhance the matching of sub-commands abbreviations: 'perf c2c rec' -> 'perf c2c record' 'perf c2c recport -> error - Set build-id using build-id header on new mmap records. - Fix generation of 'perf --version' string. perf test: - Add test for the arm_spe event. - Add test to check unwinding using fame-pointer (fp) mode on arm64. - Make metric testing more robust in 'perf test'. - Add error message for unsupported branch stack cases. libperf: - Add API for allocating new thread map array. - Fix typo in perf_evlist__open() failure error messages in libperf tests. perf c2c: - Replace bitmap_weight() with bitmap_empty() where appropriate" * tag 'perf-tools-for-v5.18-2022-03-26' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux: (143 commits) perf evsel: Improve AMD IBS (Instruction-Based Sampling) error handling messages perf python: Add perf_env stubs that will be needed in evsel__open_strerror() perf tools: Enhance the matching of sub-commands abbreviations libperf tests: Fix typo in perf_evlist__open() failure error messages tools arm64: Import cputype.h perf lock: Add -F/--field option to control output perf lock: Extend struct lock_key to have print function perf lock: Add --synth=no option for record tools headers cpufeatures: Sync with the kernel sources tools headers cpufeatures: Sync with the kernel sources perf stat: Fix forked applications enablement of counters tools arch x86: Sync the msr-index.h copy with the kernel sources perf evsel: Make evsel__env() always return a valid env perf build-id: Fix spelling mistake "Cant" -> "Can't" perf header: Fix spelling mistake "could't" -> "couldn't" perf script: Add 'brstackinsnlen' for branch stacks perf parse-events: Move slots only with topdown perf ftrace latency: Update documentation perf ftrace latency: Add -n/--use-nsec option perf tools: Fix version kernel tag ...
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‎tools/arch/arm64/include/asm/cputype.h

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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_CPUTYPE_H
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#define __ASM_CPUTYPE_H
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#define INVALID_HWID ULONG_MAX
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#define MPIDR_UP_BITMASK (0x1 << 30)
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#define MPIDR_MT_BITMASK (0x1 << 24)
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#define MPIDR_HWID_BITMASK UL(0xff00ffffff)
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#define MPIDR_LEVEL_BITS_SHIFT 3
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#define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT)
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#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
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#define MPIDR_LEVEL_SHIFT(level) \
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(((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
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#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
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((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
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#define MIDR_REVISION_MASK 0xf
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#define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK)
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#define MIDR_PARTNUM_SHIFT 4
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#define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT)
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#define MIDR_PARTNUM(midr) \
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(((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
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#define MIDR_ARCHITECTURE_SHIFT 16
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#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT)
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#define MIDR_ARCHITECTURE(midr) \
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(((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
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#define MIDR_VARIANT_SHIFT 20
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#define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT)
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#define MIDR_VARIANT(midr) \
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(((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
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#define MIDR_IMPLEMENTOR_SHIFT 24
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#define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT)
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#define MIDR_IMPLEMENTOR(midr) \
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(((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
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#define MIDR_CPU_MODEL(imp, partnum) \
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(((imp) << MIDR_IMPLEMENTOR_SHIFT) | \
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(0xf << MIDR_ARCHITECTURE_SHIFT) | \
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((partnum) << MIDR_PARTNUM_SHIFT))
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#define MIDR_CPU_VAR_REV(var, rev) \
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(((var) << MIDR_VARIANT_SHIFT) | (rev))
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#define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
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MIDR_ARCHITECTURE_MASK)
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#define ARM_CPU_IMP_ARM 0x41
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#define ARM_CPU_IMP_APM 0x50
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#define ARM_CPU_IMP_CAVIUM 0x43
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#define ARM_CPU_IMP_BRCM 0x42
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#define ARM_CPU_IMP_QCOM 0x51
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#define ARM_CPU_IMP_NVIDIA 0x4E
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#define ARM_CPU_IMP_FUJITSU 0x46
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#define ARM_CPU_IMP_HISI 0x48
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#define ARM_CPU_IMP_APPLE 0x61
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#define ARM_CPU_PART_AEM_V8 0xD0F
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#define ARM_CPU_PART_FOUNDATION 0xD00
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#define ARM_CPU_PART_CORTEX_A57 0xD07
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#define ARM_CPU_PART_CORTEX_A72 0xD08
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#define ARM_CPU_PART_CORTEX_A53 0xD03
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#define ARM_CPU_PART_CORTEX_A73 0xD09
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#define ARM_CPU_PART_CORTEX_A75 0xD0A
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#define ARM_CPU_PART_CORTEX_A35 0xD04
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#define ARM_CPU_PART_CORTEX_A55 0xD05
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#define ARM_CPU_PART_CORTEX_A76 0xD0B
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#define ARM_CPU_PART_NEOVERSE_N1 0xD0C
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#define ARM_CPU_PART_CORTEX_A77 0xD0D
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#define ARM_CPU_PART_NEOVERSE_V1 0xD40
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#define ARM_CPU_PART_CORTEX_A78 0xD41
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#define ARM_CPU_PART_CORTEX_X1 0xD44
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#define ARM_CPU_PART_CORTEX_A510 0xD46
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#define ARM_CPU_PART_CORTEX_A710 0xD47
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#define ARM_CPU_PART_CORTEX_X2 0xD48
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#define ARM_CPU_PART_NEOVERSE_N2 0xD49
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#define ARM_CPU_PART_CORTEX_A78C 0xD4B
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#define APM_CPU_PART_POTENZA 0x000
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#define CAVIUM_CPU_PART_THUNDERX 0x0A1
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#define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2
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#define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3
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#define CAVIUM_CPU_PART_THUNDERX2 0x0AF
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/* OcteonTx2 series */
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#define CAVIUM_CPU_PART_OCTX2_98XX 0x0B1
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#define CAVIUM_CPU_PART_OCTX2_96XX 0x0B2
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#define CAVIUM_CPU_PART_OCTX2_95XX 0x0B3
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#define CAVIUM_CPU_PART_OCTX2_95XXN 0x0B4
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#define CAVIUM_CPU_PART_OCTX2_95XXMM 0x0B5
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#define CAVIUM_CPU_PART_OCTX2_95XXO 0x0B6
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#define BRCM_CPU_PART_BRAHMA_B53 0x100
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#define BRCM_CPU_PART_VULCAN 0x516
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#define QCOM_CPU_PART_FALKOR_V1 0x800
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#define QCOM_CPU_PART_FALKOR 0xC00
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#define QCOM_CPU_PART_KRYO 0x200
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#define QCOM_CPU_PART_KRYO_2XX_GOLD 0x800
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#define QCOM_CPU_PART_KRYO_2XX_SILVER 0x801
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#define QCOM_CPU_PART_KRYO_3XX_SILVER 0x803
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#define QCOM_CPU_PART_KRYO_4XX_GOLD 0x804
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#define QCOM_CPU_PART_KRYO_4XX_SILVER 0x805
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#define NVIDIA_CPU_PART_DENVER 0x003
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#define NVIDIA_CPU_PART_CARMEL 0x004
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#define FUJITSU_CPU_PART_A64FX 0x001
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#define HISI_CPU_PART_TSV110 0xD01
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#define APPLE_CPU_PART_M1_ICESTORM 0x022
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#define APPLE_CPU_PART_M1_FIRESTORM 0x023
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#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
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#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
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#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
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#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
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#define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75)
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#define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35)
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#define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)
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#define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
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#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
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#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
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#define MIDR_NEOVERSE_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V1)
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#define MIDR_CORTEX_A78 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78)
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#define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1)
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#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)
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#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
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#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
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#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
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#define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
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#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
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#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
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#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
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#define MIDR_OCTX2_98XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_98XX)
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#define MIDR_OCTX2_96XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_96XX)
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#define MIDR_OCTX2_95XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XX)
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#define MIDR_OCTX2_95XXN MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXN)
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#define MIDR_OCTX2_95XXMM MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXMM)
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#define MIDR_OCTX2_95XXO MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXO)
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#define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2)
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#define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53)
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#define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)
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#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
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#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
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#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)
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#define MIDR_QCOM_KRYO_2XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_GOLD)
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#define MIDR_QCOM_KRYO_2XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_SILVER)
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#define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER)
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#define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD)
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#define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER)
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#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
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#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
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#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
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#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
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#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
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#define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
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/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
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#define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
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#define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_CPU_VAR_REV(1, 0))
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#define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_NFD1 | TCR_NFD0)
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#ifndef __ASSEMBLY__
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#include "sysreg.h"
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#define read_cpuid(reg) read_sysreg_s(SYS_ ## reg)
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/*
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* Represent a range of MIDR values for a given CPU model and a
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* range of variant/revision values.
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*
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* @model - CPU model as defined by MIDR_CPU_MODEL
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* @rv_min - Minimum value for the revision/variant as defined by
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* MIDR_CPU_VAR_REV
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* @rv_max - Maximum value for the variant/revision for the range.
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*/
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struct midr_range {
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u32 model;
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u32 rv_min;
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u32 rv_max;
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};
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#define MIDR_RANGE(m, v_min, r_min, v_max, r_max) \
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{ \
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.model = m, \
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.rv_min = MIDR_CPU_VAR_REV(v_min, r_min), \
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.rv_max = MIDR_CPU_VAR_REV(v_max, r_max), \
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}
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#define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max)
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#define MIDR_REV(m, v, r) MIDR_RANGE(m, v, r, v, r)
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#define MIDR_ALL_VERSIONS(m) MIDR_RANGE(m, 0, 0, 0xf, 0xf)
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static inline bool midr_is_cpu_model_range(u32 midr, u32 model, u32 rv_min,
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u32 rv_max)
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{
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u32 _model = midr & MIDR_CPU_MODEL_MASK;
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u32 rv = midr & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK);
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return _model == model && rv >= rv_min && rv <= rv_max;
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}
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static inline bool is_midr_in_range(u32 midr, struct midr_range const *range)
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{
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return midr_is_cpu_model_range(midr, range->model,
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range->rv_min, range->rv_max);
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}
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static inline bool
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is_midr_in_range_list(u32 midr, struct midr_range const *ranges)
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{
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while (ranges->model)
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if (is_midr_in_range(midr, ranges++))
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return true;
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return false;
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}
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/*
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* The CPU ID never changes at run time, so we might as well tell the
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* compiler that it's constant. Use this function to read the CPU ID
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* rather than directly reading processor_id or read_cpuid() directly.
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*/
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static inline u32 __attribute_const__ read_cpuid_id(void)
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{
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return read_cpuid(MIDR_EL1);
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}
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static inline u64 __attribute_const__ read_cpuid_mpidr(void)
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{
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return read_cpuid(MPIDR_EL1);
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}
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static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
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{
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return MIDR_IMPLEMENTOR(read_cpuid_id());
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}
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static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
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{
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return MIDR_PARTNUM(read_cpuid_id());
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}
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static inline u32 __attribute_const__ read_cpuid_cachetype(void)
253+
{
254+
return read_cpuid(CTR_EL0);
255+
}
256+
#endif /* __ASSEMBLY__ */
257+
258+
#endif

‎tools/arch/x86/include/asm/cpufeatures.h

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -299,9 +299,6 @@
299299
/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
300300
#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
301301
#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
302-
#define X86_FEATURE_AMX_BF16 (18*32+22) /* AMX bf16 Support */
303-
#define X86_FEATURE_AMX_TILE (18*32+24) /* AMX tile Support */
304-
#define X86_FEATURE_AMX_INT8 (18*32+25) /* AMX int8 Support */
305302

306303
/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
307304
#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
@@ -330,6 +327,7 @@
330327
#define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */
331328
#define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */
332329
#define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */
330+
#define X86_FEATURE_HFI (14*32+19) /* Hardware Feedback Interface */
333331

334332
/* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */
335333
#define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */
@@ -390,7 +388,10 @@
390388
#define X86_FEATURE_TSXLDTRK (18*32+16) /* TSX Suspend Load Address Tracking */
391389
#define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */
392390
#define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */
391+
#define X86_FEATURE_AMX_BF16 (18*32+22) /* AMX bf16 Support */
393392
#define X86_FEATURE_AVX512_FP16 (18*32+23) /* AVX512 FP16 */
393+
#define X86_FEATURE_AMX_TILE (18*32+24) /* AMX tile Support */
394+
#define X86_FEATURE_AMX_INT8 (18*32+25) /* AMX int8 Support */
394395
#define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
395396
#define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
396397
#define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */

‎tools/arch/x86/include/asm/disabled-features.h

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -56,8 +56,11 @@
5656
# define DISABLE_PTI (1 << (X86_FEATURE_PTI & 31))
5757
#endif
5858

59-
/* Force disable because it's broken beyond repair */
60-
#define DISABLE_ENQCMD (1 << (X86_FEATURE_ENQCMD & 31))
59+
#ifdef CONFIG_INTEL_IOMMU_SVM
60+
# define DISABLE_ENQCMD 0
61+
#else
62+
# define DISABLE_ENQCMD (1 << (X86_FEATURE_ENQCMD & 31))
63+
#endif
6164

6265
#ifdef CONFIG_X86_SGX
6366
# define DISABLE_SGX 0

‎tools/arch/x86/include/asm/msr-index.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -705,12 +705,14 @@
705705

706706
#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
707707
#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
708+
#define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26)
708709

709710
#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
710711

711712
#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
712713
#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
713714
#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
715+
#define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25)
714716

715717
/* Thermal Thresholds Support */
716718
#define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
@@ -959,4 +961,8 @@
959961
#define MSR_VM_IGNNE 0xc0010115
960962
#define MSR_VM_HSAVE_PA 0xc0010117
961963

964+
/* Hardware Feedback Interface */
965+
#define MSR_IA32_HW_FEEDBACK_PTR 0x17d0
966+
#define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1
967+
962968
#endif /* _ASM_X86_MSR_INDEX_H */

‎tools/include/linux/compiler.h

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -102,10 +102,6 @@
102102
# define __init
103103
#endif
104104

105-
#ifndef noinline
106-
# define noinline
107-
#endif
108-
109105
#include <linux/types.h>
110106

111107
/*

‎tools/include/linux/coresight-pmu.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,13 +18,15 @@
1818
* ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and
1919
* directly use below macros as config bits.
2020
*/
21+
#define ETM_OPT_BRANCH_BROADCAST 8
2122
#define ETM_OPT_CYCACC 12
2223
#define ETM_OPT_CTXTID 14
2324
#define ETM_OPT_CTXTID2 15
2425
#define ETM_OPT_TS 28
2526
#define ETM_OPT_RETSTK 29
2627

2728
/* ETMv4 CONFIGR programming bits for the ETM OPTs */
29+
#define ETM4_CFG_BIT_BB 3
2830
#define ETM4_CFG_BIT_CYCACC 4
2931
#define ETM4_CFG_BIT_CTXTID 6
3032
#define ETM4_CFG_BIT_VMID 7

‎tools/lib/api/fd/array.c

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -88,6 +88,23 @@ int fdarray__add(struct fdarray *fda, int fd, short revents, enum fdarray_flags
8888
return pos;
8989
}
9090

91+
int fdarray__dup_entry_from(struct fdarray *fda, int pos, struct fdarray *from)
92+
{
93+
struct pollfd *entry;
94+
int npos;
95+
96+
if (pos >= from->nr)
97+
return -EINVAL;
98+
99+
entry = &from->entries[pos];
100+
101+
npos = fdarray__add(fda, entry->fd, entry->events, from->priv[pos].flags);
102+
if (npos >= 0)
103+
fda->priv[npos] = from->priv[pos];
104+
105+
return npos;
106+
}
107+
91108
int fdarray__filter(struct fdarray *fda, short revents,
92109
void (*entry_destructor)(struct fdarray *fda, int fd, void *arg),
93110
void *arg)

‎tools/lib/api/fd/array.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,7 @@ struct fdarray *fdarray__new(int nr_alloc, int nr_autogrow);
4242
void fdarray__delete(struct fdarray *fda);
4343

4444
int fdarray__add(struct fdarray *fda, int fd, short revents, enum fdarray_flags flags);
45+
int fdarray__dup_entry_from(struct fdarray *fda, int pos, struct fdarray *from);
4546
int fdarray__poll(struct fdarray *fda, int timeout);
4647
int fdarray__filter(struct fdarray *fda, short revents,
4748
void (*entry_destructor)(struct fdarray *fda, int fd, void *arg),

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